Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-06-08
2008-03-04
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185230, C365S233100, C365S194000, C365S185140
Reexamination Certificate
active
07339827
ABSTRACT:
In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.
REFERENCES:
patent: 4344154 (1982-08-01), Klaas et al.
patent: 5187683 (1993-02-01), Gill et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 5991204 (1999-11-01), Chang
patent: 6111789 (2000-08-01), Choi et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6807105 (2004-10-01), Ogura et al.
patent: 7132718 (2006-11-01), Hisamoto et al.
patent: 2001/0050862 (2001-12-01), Nakamura
patent: 2001/0054737 (2001-12-01), Nakamura et al.
patent: 2004/0119107 (2004-06-01), Hisamoto et al.
patent: 2005/0226055 (2005-10-01), Guterman
patent: 5-048113 (1993-02-01), None
patent: 5-121700 (1993-05-01), None
patent: 07030076 (1995-01-01), None
patent: 2004-186452 (2004-07-01), None
A JPO computer translation of JP 07030076 A.
Kianian et al., “A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2Prom”,1994 Symposium on VLSI Technology Digest of Technical Papers, 1994, pp. 71-72.
Chen et al., “A Novel Flash Memory Device with SPlit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”,1997 Symposium on VLSI Technology Digest of Technical Papers, 1997, pp. 63-64.
Hisamoto Digh
Tanaka Toshihiro
Yamaki Takashi
Yasui Kan
Hur J. H.
Miles & Stockbridge P.C.
Renesas Technology Corp.
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