Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-09-06
2002-04-09
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S145000
Reexamination Certificate
active
06370058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory device including a memory cell having volatile and non-volatile data storage capacity. More particularly, the present invention relates to a Non-Volatile Dynamic Random Access Memory (hereinafter referred to as “NVDRAM”) including a memory cell having a combination of a Dynamic Random Access Memory (hereinafter referred to as “DRAM”) as a volatile data storage means and a Electrically Erasable and Programmable Read Only Memory (hereinafter referred to as “EEPROM”) as a non-volatile data storage means, or a memory cell having volatile and non-volatile data storage capacity using a ferroelectric material. Further, the present invention relates to a system Large-Scale Integrated circuit (hereinafter referred to as “LSI”) such as a system control circuit or system solution chip; a system Center Processing Unit (hereinafter referred to as “CPU”); a system Multi Processing Unit (hereinafter referred to as “MPU”); and the like.
2. Description of the Related Art
Conventional NVDRAMs are typically categorized into two types. One type includes a combination of a DRAM and a EEPROM. The other type employs a ferroelectric material.
The structure and operation of the DRAM and EEPROM combination type NVDRAMs are described in “A 256 K-bit Non-Volatile PSRAM with Page Recall and Chip Store”, 1991 Sym. VLSI Circuit Dig. Tech. Papers, May, pp. 91-92, and in “Development of 256 K bit Non-Volatile DRAM (NV-DRAM) Operating as a Pseudo-SRAMR”, Sharp Technical Journal, No. 49, pp. 45-49, June, 1991.
In a normal volatile (DRAM) operation, the DRAM and EPPROM combination type NVDRAM uses its DRAM for data access. In a store operation, immediately before the NVDRAM is turned off or at any time desired, data held in the DRAM is transferred to the EEPROM. In the recall operation, the data stored in the non-volatile state is transferred from the EEPROM to the DRAM.
As a result, a high-speed data access can be achieved by the DRAM in the normal DRAM operation while the data can be saved safely in the EEPROM in the absence of supplied power. The advantages of the combination type NVDRAM are that data can be retained separately in the DRAM and the EEPROM; and that there is no limitation to the number of times the recall operation can be repeated.
On the other hand, a ferroelectric type NVDRAM is described in (1) “An Experimental 512-bit Non-Volatile Memory with Ferroelectric Storage cell”, IEEE Journal of Solid State Circuites, Vol. 23, pp. 1171-1175, October, 1988; (2) “A Ferroelectric DRAM Cell for High-Density NVRAM's”, IEEE Electron Device Lett. Vol. 11, No. 10, pp. 454-456, October, 1990; and (3) Japanese Laid-Open Publication No. 4-42498, “A Semiconductor Memory Device, and a Method for Read/Write the Semiconductor Memory Device”.
Article (1) describes a ferroelectric type NVDRAM as including memory cells each having two transistors and two capacitors (hereinafter this type of NVDRAM will be referred to as a two-transistor/cell NVDRAM). In the two-transistor/cell NVDRAM, a read/write operation is performed in a recall/store mode which involves polarization reversal of a ferroelectric thin film included in the memory cell. However, the two-transistor/cell NVDRAM cannot satisfy the required number of available polarization reversals (10
15
to 10
16
times) of the ferroelectric thin film in order to achieve 10-year continuous operation with a cycle of 100 nsec. This is because the possible number of the available polarization reversals of the ferroelectric thin film is limited to 10
12
to 10
13
times at maximum under the preset situation. Article (2) discusses the difference in fatigue of the ferroelectric thin film operated during a volatile (DRAM) operation without the polarization reversal and during a non-volatile (recall/store) operation. It is reported that the fatigue of the ferroelectric thin film is significantly small during the volatile operation compared with during the non-volatile operation. Article (3) describes an example of a non-volatile semiconductor memory device including word lines selected by row addresses and plate lines and sense amplifiers selected by column addresses, realizing low power consumption and a short cycle.
The above-mentioned ferroelectric type NVDRAMs use memory cells each incorporating a capacitor element which has a thin film made of a ferroelectric material with a crystal structure of a perovskite type, e.g., Y
1
(the common name of a ferroelectric ceramic which is less fatigued by a rewrite operation (polarization reversal)), PZT, PLZT, PbTiO
3
, etc. Many kinds of ferroelectric materials have been vigorously developed in order to realize an ideal ferroelectric thin film which is not fatigued by the polarization reversal and which has a large remanent polarization and a large dielectric constant.
When an AC voltage is applied to the capacitor element including such a ferrroelectric thin film, the polarization of the ferroelectric thin film shows a hysteresis characteristic as shown in FIG.
11
. As seen from
FIG. 11
, the polarization state of the ferroelectric material, which is at point A when it is not polarizaed, shifts to point B when a positive electric field is applied to the ferroelectric thin film. The polarization state of the ferroelectric thin film returns only to point C (instead of A) when the electric field is removed, thus resulting in a positive remanent polarization. This remanent polarization vanishes when a negative electric field is applied. By further increasing the intensity of the negative electric field, the polarization of the ferroelectric thin film is reversed so that the polarization state shifts to point D. The polarization state of the ferroelectric thin film returns only to point E when the electric field is again removed, thus resulting in a negative remanent polarization. Thus, by allowing the polarization of the ferroelectric thin film to be reversed so as to attain positive or negative remanent polarization, given data can be stored in a non-volatile manner. Moreover, by simply applying or removing a positive or negative electric field across the capacitor element, it can be ensured that the polarization state of the ferroelectric material of the capacitor element shifts only between points B and C or between points D and E, instead of having polarization reversals. Thus, given data can be stored in a volatile manner, as in the case of a usual DRAM.
The above-described ferroelectric NVDRAM has the advantage that, since the memory cells thereof can be constituted by a smaller number of elements than in the case of a combination type NVDRAM, the cell areas can be reduced, thereby providing for further integration of the device. The ferroelectric NVDRAM has another advantage of low power consumption.
Hereinafter, the structure and operation of an exemplary ferroelectric type NVDRAM, where two-transistor/cell memory cells are used, will be described. The two transistor/cell memory cell is known to be immune to possible variations in the fabrication process.
As shown in
FIG. 12
, this ferroelectric type NVDRAM includes a plurality of word lines WL and corresponding plate lines PT. The word lines WL are connected to a word line decoder
31
. The plate lines PT are connected to a plate decoder
32
. The NVDRAM also includes a plurality of pairs of bit lines, bit and bit-bar. Each pair of bit lines, bit and bit-bar, are connected to a sense amplifier
33
. In
FIG. 12
, only one pair of bit lines, bit and bit-bar, and their corresponding sense amplifier
33
are shown.
A memory cell
34
is provided in each portion where one of the word lines WL and its corresponding plate line PT intersect a pair of bit lines, bit and bit-bar. In
FIG. 12
, only one memory cell
34
is shown. The memory cell
34
includes two capacitor elements C
1
and C
2
and two selection transistors Q
1
and Q
2
. One of the terminals of the capacitor element C
1
is connected to the bit line bit via the transistor Q
1
. One of the terminals of
Ho Hoai V.
Sharp Kabushiki Kaisha
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