Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-09-03
2004-11-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185210, C365S185200, C365S185240
Reexamination Certificate
active
06816409
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method for rewriting data thereto. More particularly, the present invention relates to a non-volatile semiconductor memory device suitable for multi-value flash memories, such as flash EEPROM (Electrically Erasable and Programmable Read Only Memory) and the like, and a method for rewriting data thereto.
2. Description of the Related Art
Conventionally, an electrically rewritable non-volatile semiconductor memory device, such as EEPROM, flash EEPROM, and the like, comprises a memory array in which a plurality of memory cell transistors, each of which comprises a charge accumulation layer comprising a floating gate and an insulating film between a control gate and a semiconductor substrate, are provided.
By injecting electric charges into the charge accumulation layer or discharging electric charges from the charge accumulation layer, the threshold voltage Vth of the memory cell transistor is changed. By changing the threshold voltage Vth of the memory cell transistor in that manner, data is written into the memory cell transistor and the memory cell transistor stores the written data.
In order to write data into the memory cell transistor, for example, a voltage of 0 V is applied to a source diffusion region provided in the semiconductor substrate, a voltage of about 5 V is applied to a drain diffusion region, and a pulse voltage of about 12 V is applied to the control gate. In this case, the floating gate is not electrically fixed and is floating.
When a pulse voltage is applied to the control gate, the memory cell transistor is turned ON so that an electric current flows between the source and the drain. The electric current generates hot electrons. The hot electrons (i.e., electric charges) are injected into the floating gate and are accumulated therein. When the electrons are injected into the floating gate, the threshold voltage Vth of the memory cell transistor controlled by the control gate is increased. By associating the threshold voltage Vth with data “1” or “0”, two-value data can be stored in the memory cell transistor.
FIG. 9
is a graph showing the threshold voltage distribution of memory cell transistors in a two-value memory.
FIG. 9
shows the threshold voltage distribution of memory cell transistors when electrons are not injected into the floating gates thereof (corresponding to the left-hand distribution indicated by reference numeral
92
) and the threshold voltage distribution of memory cell transistors when electrons are injected to the floating gates thereof (corresponding to the right-hand distribution indicated by reference numeral
94
). Note that in the graph of
FIG. 9
, the horizontal axis represents the threshold voltage Vth of a memory cell transistor, while the vertical axis represents the number of memory cell transistors indicating a threshold voltage Vth (i.e., the number of bits).
One data value corresponds to one threshold voltage distribution. Threshold voltages corresponding to one data value are distributed in a certain range. As used herein, such a range is referred to as threshold voltage range.
The threshold voltage of a memory cell transistor is relatively low, as indicated by reference numeral
92
, when electric charges are not injected into the floating gate thereof. The threshold voltage of a memory cell transistor is relatively high, as indicated by reference numeral
94
, when electric charges are injected into the floating gate thereof.
Therefore, when a determination voltage which is located between the two threshold voltage ranges is applied to the control gate, a memory cell transistor whose floating gate does not receive injected electric charges (i.e., a memory cell transistor having the distribution indicated by reference numeral
92
) is turned ON and a read electric current flows therethrough, and a memory cell transistor whose floating gate receives injected electric charges (i.e., a memory cell transistor having the distribution indicated by reference numeral
94
) is turned OFF and a read electric current does not flow therethrough.
By detecting the presence or absence of the read electric current using a sense circuit, the sense circuit can read out data stored in a memory cell transistor as “0” or “1”, depending on the threshold voltage thereof. Thus, the ON/OFF state of a memory cell transistor is changed depending on a change in threshold voltage caused by electric charge injection into the charge accumulation layer (more specifically, floating gate) of the memory cell transistor, so that the threshold voltage of the memory cell transistor can be associated with data.
In recent years, a so-called multi-value memory technology has been proposed in which by regulating the amount of electric charges injected into a floating gate, more data values can be written into one memory cell transistor.
Such a multi-value flash memory is described in, for example, “IEEE Journal of Solid-State Circuits Vol. 31, No. 11”, November 1996, pp. 1575-1583. In the case of a four-value memory, for example, there are four threshold voltage distributions. Three determination voltages, each of which is located between two adjacent threshold voltage distributions among the four threshold voltage distributions, are applied to a word line connected to a control gate. Specifically, three read operations are carried out. In this case, an operation similar to the read operation of the two-value memory is carried out three times while changing the value of a determination voltage applied to a word line.
FIG. 10
is a graph showing the distribution of the threshold voltages Vth of memory cell transistors in a four-value memory. Note that in
FIG. 10
, the horizontal axis represents the threshold voltage Vth of a memory cell transistor, while the vertical axis represents the number of memory cell transistors indicating a threshold voltage Vth (i.e., the number of bits).
The threshold voltage of a memory cell transistor whose floating gate does not receive injected electric charges is relatively low as indicated by the left-hand most distribution in
FIG. 10
(reference numeral
102
). The threshold voltages of memory cell transistors whose floating gate receives injected electric charges are relatively increased with an increase in the amount of electric charges injected into the floating gate as indicated by right-hand distributions in
FIG. 10
(reference numerals
104
,
106
, and
108
).
It is now assumed that a certain determination voltage is applied to the control gate. If the threshold voltage of a memory cell transistor is lower than the determination voltage, the memory cell transistor is turned ON and a read electric current flows therethrough. If the threshold voltage of a memory cell transistor is higher than the determination voltage, the memory cell transistor is turned OFF and a read electric current does not flow therethrough. The three determination voltages are each applied, and the presence or absence of a read electric current is detected using a sense circuit. Thus, data stored in the memory cell transistor can be read, i.e., it can be determined which value the data has among the four values.
In general, the following phenomenon is known. Electrons are injected into the floating gate of a memory cell transistor so that the threshold voltage Vth of a memory cell transistor is increased to a prescribed value. Thereafter, the memory cell transistor is allowed to be idle. As the idle time is increased, the threshold voltage Vth of the memory cell transistor is shifted toward a lower value.
FIG. 11
is a graph showing that the threshold voltage Vth of a memory cell transistor is shifted as the idle time t of the memory cell transistor is increased. Note that in
FIG. 11
, the horizontal axis represents an idle time t, while the vertical axis represents a threshold voltage Vth.
As shown in
FIG. 11
, when the idle time of a memory cell transistor reaches t0, the threshold voltage Vth of the memor
Morrison & Foerster / LLP
Phan Trong
Sharp Kabushiki Kaisha
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