Non-volatile semiconductor memory device and method of...

Details Non-volatile semiconductor memory device and method of... Non-volatile semiconductor memory device and method of...

2008-12-05

2010-11-02

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

07826270

ABSTRACT:
MOS transistors each having different ON withstanding voltages that are drain withstanding voltages when gates thereof are turned on are formed on the same substrate. One of the MOS transistors having the lower ON withstand voltage is used as a memory element. Using the fact that the drain withstanding voltage is low when a gate thereof is turned on, a short-circuit occurs in a PN junction between a drain and the substrate of the one of the MOS transistors having the lower ON withstand voltage to write data.

REFERENCES:
patent: 7088620 (2006-08-01), Kawai et al.
patent: 7180796 (2007-02-01), Tanzawa et al.
patent: 7212443 (2007-05-01), Furuyama
patent: 7688631 (2010-03-01), Kim et al.
patent: 6-139778 (1994-05-01), None
patent: 10-189918 (1998-07-01), None

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4187578