Non-volatile semiconductor memory device and method for manufact

Details Non-volatile semiconductor memory device and method for manufact Non-volatile semiconductor memory device and method for manufact

1995-06-07

1998-01-27

Fourson, George R.

Fishing, trapping, and vermin destroying

437 29, 437 52, H01L 218247

Patent

active

057121788

ABSTRACT:
An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.

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