Non-volatile semiconductor memory device and method for erasure

Details Non-volatile semiconductor memory device and method for erasure Non-volatile semiconductor memory device and method for erasure

1994-11-29

1996-07-09

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518528, 36518533, G11C 700

Patent

active

055351581

ABSTRACT:
A non-volatile memory cell disclosed herein includes a pair of regions are provided in a channel region in contact respectively with source and drain to provide a symmetrical structure. A data erase is done by applying a high voltage to the source to produce avalanche breakdown between the source and the region to inject induced hot carriers into the floating gate and wherein the memory cell threshold voltage after erasure is converged to a constant value irrespective of the initial states, while the converged value may be controlled to a desired voltage by applying a suitable voltage to the control gate. Erasure sequence consisting in all bit erase and one verification is sufficient such that the erase sequence is simplified and erase time shortened.

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Yamada et al.; "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM"; IEDM '91, pp. 307-309.

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