Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-06-26
2001-10-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S185180, C365S185240
Reexamination Certificate
active
06310800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to mask type and floating gate electrode type non-volatile semiconductor memory devices and a method for driving the same.
2. Description of the Related Art
In recent years, a non-volatile semiconductor memory device which operates at a low voltage and a high speed has been utilized. In order to widely provide such a non-volatile semiconductor memory device, there is a demand for a non-volatile semiconductor memory device capable of operating at a low voltage and a high speed, and a method for driving the same.
Hereinafter, a conventional non-volatile semiconductor memory device
500
will be described with reference to
FIGS. 15
,
16
, and
17
.
The non-volatile semiconductor memory device
500
has a NOR type memory cell array structure, in which a plurality of memory cells are connected in parallel to bit lines.
FIG. 15
is a schematic diagram showing a structure of a memory cell array of the non-volatile semiconductor memory device
500
.
The non-volatile semiconductor memory device
500
shown in
FIG. 15
includes memory cells M
11
through M
44
composed of MOS transistors, word lines WL
1
through WL
4
, source lines SL
1
through SL
3
, and bit lines BL
1
through BL
4
.
In the non-volatile semiconductor memory device
500
, as shown in
FIG. 15
, a gate of the memory cell M
24
is connected to the word line WL
2
, a source of the memory cell M
24
is connected to the source line SL
2
, and a drain of the memory cell M
24
is connected to the bit line BL
4
. In the non-volatile semiconductor memory device
500
, the memory cells M
21
through M
24
and the memory cells M
31
through M
34
share the source line SL
2
. The memory cells M
11
through M
14
and the memory cells (not shown) opposed thereto share the source line SL
1
. This is also applicable to the source line SL
3
.
FIG. 16
is a schematic plan view showing a layout pattern of the non-volatile semiconductor memory device
500
shown in FIG.
15
.
As shown in
FIG. 16
, the non-volatile semiconductor memory device
500
includes isolation regions
5
and bit line contacts
6
.
Hereinafter, a write method and a read method of the non-volatile semiconductor memory device
500
will be described with reference to FIG.
17
.
FIG. 17
shows a threshold voltage distribution diagram of memory cells in the non-volatile semiconductor memory device
500
. In
FIG. 17
, the abscissa represents a threshold voltage V
TM
of the memory cells, and the ordinate represents the number of memory cells.
It is assumed herein that the non-volatile semiconductor memory device
500
is a mask ROM composed of N-type MOS transistors having two different threshold voltages.
An erase state (“E” state in
FIG. 17
) refers to that N-type MOS transistors are set at a threshold voltage (lower threshold voltage) of about 1 volt, in which the N-type MOS transistors are in an enhancement state. The erase state is controlled by ion implantation to the channel portions of memory cells in the entire memory array.
A write state (“W” state in
FIG. 17
) refers to that ions are additionally implanted only to the channels of selected N-type MOS transistors, whereby the selected N-type MOS transistors are set at a threshold voltage (higher threshold voltage) of about 4 volts, which is higher than a supply voltage V
DD
and in which the N-type MOS transistors are in an enhancement state.
Hereinafter, a read method of the non-volatile semiconductor memory device
500
will be described with reference to FIG.
15
.
In the case where the memory cell M
24
surrounded by a broken line in
FIG. 15
is selected, an electric potential of a semiconductor substrate is set at a ground voltage (0 volts), the word line WL
2
is set at about 3 volts, and the bit line BL
4
is set at about 1 volt, respectively. Furthermore, the other word lines WL
1
, WL
3
, and WL
4
, the source lines SL
1
through SL
3
, and the other bit lines BL
1
, BL
2
, and BL
3
are set at about 0 volts or set to be an OPEN state. The semiconductor substrate on which a memory array is arranged in
FIG. 15
is fixed at a ground voltage, based on which a voltage is applied to the other portions.
If the memory cell M
24
is in an erase state, the threshold voltage thereof is set at about 0.5 volts. Therefore, the memory cell M
24
turns on, and a current for reading information from the memory cell flows through the bit line BL
4
. On the other hand, if the memory cell M
24
is in a write state, the threshold voltage thereof is set at about 4 volts. Therefore, the memory cell M
24
turns off, and a current for reading information from the memory cell does not flow through the bit line BL
4
. The amount of the current is detected by a sense amplifier, and a read operation is performed.
As described above, the information stored in the selected memory cell M
24
is read by using the amount of the current for reading the information from the memory cell which flows through the memory cell M
24
. Therefore, it is required that currents flowing from the non-selected memory cells M
14
, M
34
, and M
44
connected to the bit line BL
4
to which the memory cell M
24
is also connected are set at about 0. In order to do this, the threshold voltages of these non-selected memory cells are required to be set at about 0.5 volts or higher.
However, in the non-volatile semiconductor memory device
500
and the method for rewriting information using the same, the threshold voltage of a memory cell in an erase state (i.e., the lower threshold voltage) is set at about 0.5 volts or higher. Therefore, if the non-volatile semiconductor memory device
500
is operated at a low voltage (lower supply voltage), the amount of a current for reading information from the memory cell in an erase state (ON state) becomes small during reading, making it difficult to read information at a high speed.
SUMMARY OF THE INVENTION
A non-volatile semiconductor memory device of the present invention includes, on a semiconductor substrate, a plurality of memory cells arranged in a matrix, a plurality of word lines extending in a row direction, a plurality of source lines extending in the row direction, and a plurality of bit lines extending in a column direction, wherein a plurality of memory cells belonging to a certain row are connected to a first source line among the plurality of source lines, a plurality of memory cells belonging to a row adjacent to the certain row are connected to a second source line among the plurality of source lines, and the first source line is electrically independent from the second source line.
In one embodiment of the present invention, the first source line is insulated from the second source line by an isolation region.
A non-volatile semiconductor memory device of the present invention includes, on a semiconductor substrate, a plurality of memory cells arranged in a matrix, a plurality of word lines extending in a row direction, a plurality of source lines extending in the row direction, and a plurality of bit lines extending in a column direction, wherein a first group among a plurality of memory cells belonging to a certain column are connected to a first bit line among the plurality of bit lines, a second group among a plurality of memory cells belonging to the certain column are connected to a second bit line among the plurality of bit lines, and the first bit line is electrically independent from the second bit line.
In one embodiment of the present invention, the first group is adjacent to the second group in the column direction.
In another embodiment of the present invention, each of the plurality of memory cells is a MOS transistor having a gate electrode, a gate insulating film, a drain region, and a source region.
In another embodiment of the present invention, each of the plurality of memory cells is a floating gate electrode type MOS transistor having a control gate electrode, a floating gate electrode, a drain region, and a source region
Auduong Gene N.
Matsushita Electronics Corporation
Nelms David
Renner , Otto, Boisselle & Sklar, LLP
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