Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-06-28
2004-06-15
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S185110, C365S230080
Reexamination Certificate
active
06751153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically writable/erasable non-volatile semiconductor memory device, and an information apparatus using the same. More particularly, the present invention relates to a non-volatile semiconductor memory device which electrically executes data read, write and erase operations separately, such as flash EEPROM (flash memory), and the like, and an information apparatus using the same.
2. Description of the Related Art
In conventional electrically writable/erasable flash memories, the electrode voltage of each selected transistor in memory cells subjected to a data write/erase operation is in a write/erase mode in which the voltage is suited to the write/erase operation. In memory cells subjected to an electrical read operation, the electrode voltage of each transistor in selected memory cells is in a read mode in which the voltage is suited to the read operation.
Typically, the write/erase mode and the read mode have to have a different applied electrode voltage. Therefore, it is difficult to allow memory cells in the write/erase mode and memory cells in the read mode to coexist in the same memory block. For this reason, dual work flash memories have been widely developed and used.
The dual work flash memory comprises a plurality of memory banks including some memory blocks. While one of a plurality of memory banks is subjected to a write/erase operation, a read operation is carried out for another memory bank, thereby achieving a so-called dual work operation.
In the dual work flash memory, the memory bank of the write/erase operation and the other memory bank of the read operation have to be controlled by separate address signals.
This is because an address signal input for the read operation has to avoid affecting the write/erase operation executed in the other memory bank. Therefore, the dual work flash memory has to have address signals on at least two lines (at least two sets of address signals).
An example of the address control of the dual work flash memory will be described with reference to
FIG. 9
which shows major portions of the dual work flash memory.
In
FIG. 9
, the dual work flash memory has input buffer
21
, an address control circuit
22
, a command recognition section
23
, a write/erase control circuit
24
, two memory banks a and b, a decoder circuit
25
connected to memory bank a, and a decoder circuit
26
connected to memory bank b.
An address signal A is input to the input buffer
21
from an external address pad (not shown).
An address signal Abuf is input to the address control circuit
22
from the input buffer
21
.
A command signal C is input to the command recognition section
23
. When the command recognition section
23
recognizes the signal as a valid command, the command recognition section
23
outputs a latch control signal Clatch to the address control circuit
22
, and a control signal Cwsm identifying the type of the command from the command recognition section
23
to the write/erase control circuit
24
.
To the write/erase control circuit
24
, a bank signal Cbank
1
described below is input from the address control circuit
22
, and the control signal Cwsm is input from the command recognition section
23
. The write/erase control circuit
24
outputs write/erase control signals Ca and Cb.
To the decoder circuit
25
, an address signal Aa is input from the address control circuit
22
, and the write/erase control signal Ca is input from the write/erase control circuit
24
.
To the decoder circuit
26
, an address signal Ab is input from the address control circuit
22
, and the write/erase control signal Cb is input from the write/erase control circuit
24
.
Hereinafter, the address control circuit
22
which outputs the address signals Aa and Ab which correspond to the above-described address signal on two lines will be described in detail with reference to FIG.
10
.
As shown in
FIG. 10
, the address control circuit
22
has an address latch circuit
31
controlled by the latch control signal Clatch, a bank decoder
32
which decodes the received address signal Abuf so as to indicate which memory bank an address is directed to, a latch circuit
33
which is controlled by the latch control signal Clatch and stores a bank signal Cbank decoded by the bank decoder
32
, and a multiplexer circuit
34
which is controlled by the bank signal Cbank
1
stored by the latch circuit
33
and performs connection control so that an address signal Alatch latched by the address latch circuit
31
and the address signal Abuf correspond to the address signals Aa and Ab on the two lines. The bank signal Cbank
1
is also output to the write/erase control circuit
24
.
It should be noted that general flash memories further include a data signal carrying information to be written, a sense circuit for reading information stored in memory cells, various circuits for high voltage (hereinafter also referred to as a high-voltage-related circuit), such as a booster circuit and the like. These are not specifically involved in the present invention and therefore are not shown. The structure and operation of such elements are not described unless particularly required.
Hereinafter, for example, a description is given of address control when data is read from memory bank b while data is written to memory bank a.
When the dual work flash memory is instructed to write data to memory bank a, the command signal C represents a command of a write operation, and the address signal A represents an address in memory bank a.
The command signal C is recognized (identified) by the command recognition section
23
as a write command, and activates the latch control signal Clatch. Further, control signal Cwsm informs the write/erase control circuit
24
that the input command is a write command.
On the other hand, the input buffer
21
receives the address signal A and transfers the address signal Abuf to the address control circuit
22
. The address control circuit
22
receives the activated latch control signal Clatch from the command recognition section
23
, and causes the address signal Abuf to be stored in the address latch circuit
31
.
Further, the bank decoder
32
decodes the input address signal Abuf so as to indicate which bank the address represented by the input address signal Abuf is directed to (i.e., whether the address is in memory bank a or memory bank b). Assuming that memory banks a and b have the same memory capacity (the size of address space), and a memory map as shown in
FIG. 11
, the address signal Abuf designates memory bank a when the most significant bit of the address is “0”, while the address signal Abuf designates memory bank b when the most significant bit of the address is “1”.
The bank signal Cbank decoded by the bank decoder
32
is stored in the latch circuit
33
in response to the activation of the latch control signal Clatch.
Further, based on the bank signal Cbank
1
stored by the latch circuit
33
, the multiplexer circuit
34
performs connection control so that the address signal Alatch stored in the address latch circuit
31
and address signal Abuf correspond to the respective address signals Aa and Ab.
The above-described operations connect signal lines so that the address signal Alatch stored in the address latch circuit
31
corresponds to the address signal Aa directed to memory bank a, while the address signal Abuf output from the input buffer
21
corresponds to the address signal Ab directed to memory bank b.
The write/erase control circuit
24
receives the bank signal Cbank
1
, activates the write/erase control signal Ca directed to memory bank a, and controls the decoder circuit
25
so that memory cells selected by the address signal Aa in memory bank a are caused to be in the write mode.
The address signal Ab to memory bank b is logically and electrically separated from the address signal Aa to memory bank a by the multiplexer circuit
34
in the address control circuit
22
. The address signal Ab is also connected to corres
Fukui Haruyasu
Mori Yasumichi
Sumitani Ken
Tanaka Yuji
Mai Son
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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