Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-09-02
2004-10-26
Pham, Hoai (Department: 2814)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260
Reexamination Certificate
active
06809966
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, more particularly, to a flash/EEPROM in a semiconductor device and a fabricating method thereof.
2. Background of the Related Art
EEPROM is characterized in two categories: a byte erasure type and a flash type. The flash type is further divided into a hot-electron injection type and a F-N (Fowler-Nordhein) current type. An EEPROM/flash type memory device is basically constructed with a MOS transistor having stacked polysilicon gates including a floating gate and a control gate. When there are no electrons in the floating gate, a channel for current to flow through is generated as voltage is applied to the control gate and the voltage applied to the control gate exceeds a threshold voltage to form the channel. When electrons are accumulated in the floating gate, the voltage applied to the control gate forms the channel at a higher level than when there are no electrons in the floating gate because of an electric field offset effect due to the negative charges in the floating gate.
A semiconductor non-volatile memory operates by the principle that electrons accumulated in the floating gate will be unable to escape when an energy barrier exists in both the silicon substrate and the control gate. Electron injection and discharge are performed on a floating gate of a semiconductor non-volatile memory to make the memory electrically rewritable where the threshold voltage of a memory cell increases proportionally with the amount of injected electrons. A non-volatile memory in a semiconductor device is enabled by designating an electron-accumulated state as ‘1’ and a non-electron state as ‘0’ because electrons accumulated around the floating gate do not escape and external electrons do not enter into the floating gate.
A basic structure of a stacked gate, which introduces no selection gate, is similar to a UV-erasing type memory device and is particularly useful for fabricating a highly-integrated memory device. Erasing is achieved by having a control gate, which is either grounded or receiving a negative voltage, and applying a high voltage to a source, resulting in a F-N current between the source and a floating gate thus decreasing the threshold voltage. Alternatively, a negative voltage may be applied to the substrate for a blanket erasing.
Source/drain regions of a non-volatile memory device such as an EEPROM are impurity diffusion regions doped heavily with impurities, while a channel region is formed in an active area of a substrate over which the floating and control gates overlap each other.
Cell programming is achieved by injecting hot channel electrons, which are generated from a drain stage of the channel region by applying a predetermined voltage to the control gate and the drain region, respectively, into a floating gate. Programming is achieved by hot channel electron injection so that the hot carriers generated near the drain are injected into the floating gate from the drain, provided that the channel region is inversed by applying a high voltage to the control gate and applying a proper voltage to the drain, where the source and well are grounded. Erasing is achieved by discharging carriers stored in the floating gate. Erasing of an EEPROM is completed by U-V erasure or by applying a high voltage to the source or drain regions or the bulk. Reading is achieved by judging a cell status of on/off by means of reading the threshold voltage of a cell transistor. For instance, once the control gate and the drain are supplied with 5V and 1V respectively, the threshold voltage of the programmed cell becomes high (at least over 5V) to be ‘off’, while the erased cell becomes low to be ‘on’. In other words, EEPROM (electrically erasable and programmable read only memory) enables data to be programmed and erased electrically, which means that EEPROM installed in a system enables the system to rewrite data with ease.
Flash EEPROM developed from EEPROM enables programming of data by a byte or more according to the design and to erase data by bits or a block, thereby improving the operating speed of EEPROM greatly. Accordingly, a non-volatile flash memory device, of which integration is superior to that of EEPROM, meets the needs of a high capacity memory device and enables high speed data reading operation for portable office automation. However, a flash memory device of 1 Tr type (ETOX) fabricated by the related art consumes electric current excessively, thereby requiring an oversized voltage pump circuit. And, the flash memory device according to the related art requires an additional circuit for preventing electrical disturbance if a selection gate is not introduced. Moreover, the more frequently the device is used, the less reliable the flash memory device according to the related art becomes because of the limited endurance of programming and erasing.
FIG.
1
A and
FIG. 1B
show cross-sectional views seen from the directions of channel length and width, respectively, of an EEPROM device in a semiconductor device fabricated by a related art. In
FIGS. 1A-1B
, a field oxide layer
11
defining a device isolation area and a device active area are formed by LOCOS (local oxidation of silicon) on predetermined portions of a silicon substrate
10
, thereby exposing the device active area. In the active area of the substrate
10
, a gate insulating layer
12
formed of oxide, a floating gate
13
formed of polysilicon on the gate insulating layer
12
, an inter-poly layer
14
formed of an insulator of an O—N—O structure, and a control gate
15
of polysilicon are formed.
A method of fabricating a non-volatile memory device according to the related art includes forming a second conductive type well in a predetermined portion of a first conductive type silicon substrate
10
, then forming by LOCOS a field oxide layer
11
, which acts as a device isolation layer. Next, a gate oxide layer
12
is formed by oxidizing a surface of the substrate
10
thermally and a polysilicon layer is deposited on the gate oxide layer
12
, followed by the formations of a floating gate
13
by patterning the polysilicon layer and the gate insulating layer so that the polysilicon layer and the gate insulating layer remain within a memory cell only. An O—N—O layer
14
is then formed on an exposed top surface of the floating gate
13
.
After an upper polysilicon layer has been deposited on the substrate including the surface of the O—N—O layer
14
, where the O—N—O layer
14
acts as an insulating layer between the polysilicon layers, a control gate
15
is formed in a direction along the length of the channel by patterning the upper polysilicon layer to extend to another memory cell. Then, an impurity diffusion region
16
is formed by implanting first conductive type impurity ions, where the control gate
15
is used as a mask, then diffusing the impurity ions to form source and drain regions
16
. In this case, the impurity diffusion regions
16
may be formed with either a symmetrical junction or an asymmetrical junction, where the symmetrical junction is used for a negative erase while the asymmetrical junction used for a positive erase.
As mentioned in the above description of the non-volatile memory device (of a single poly gate type EEPROM) fabricated by the related art, the area occupied by a cell with a single gate is relatively large and the voltage applied for programming and erasing operations carried out by F-N tunneling is relatively high. Moreover, in a split gate type EEPROM constructed with 2 or 3 gates according to the related art, programming and erasing are achieved by the injection of hot electrons and by F-N tunneling, respectively. Namely, the split gate type introduces a structure where the control gate covers the floating gate.
As described above, the related art EEPROM have various disadvantages. The split-gate type EEPROM according to the related art produces disturbances and consumes lots of power when a programming
Fleshner & Kim LLP
LG Electronics Inc.
Pham Hoai
LandOfFree
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