Non-volatile semiconductor memory device and erasing method...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185200

Reexamination Certificate

active

07974135

ABSTRACT:
A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit.

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patent: 7272050 (2007-09-01), Han et al.
patent: 7480178 (2009-01-01), Park et al.
patent: 7593259 (2009-09-01), Kim
patent: 2006/0034128 (2006-02-01), Han et al.
patent: 2005-235260 (2005-09-01), None

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