Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-05-02
2006-05-02
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
07038951
ABSTRACT:
A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.
REFERENCES:
patent: 6457126 (2002-09-01), Nakamura et al.
patent: 6542410 (2003-04-01), Hirano
patent: 09-320282 (1997-12-01), None
Hirano Yasuaki
Kouchi Shuichiro
Le Thong Q.
Sharp Kabushiki Kaisha
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