Non-volatile semiconductor memory device and electric device...

Details Non-volatile semiconductor memory device and electric device... Non-volatile semiconductor memory device and electric device...

2005-11-22

2005-11-22

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S185170, C365S230060

Reexamination Certificate

active

06967894

ABSTRACT:
A non-volatile semiconductor memory device has a memory core circuit including a cell array in which electrically rewritable and non-volatile memory cells are arranged therein, decoders configured to select the memory cells, and sense amplifiers configured to perform data read and write of the cell array, and a peripheral circuit including a memory controller configured to control data read and write in communication with the memory core circuit, wherein the memory controller has: an oscillator configured to generate an internal clock signal; a timing control circuit configured to timing control timings of data read and write of the cell array as synchronous with the internal clock signal; and a merge clock generation circuit configured to generate based on an external timing signal and the internal clock signal a merge clock signal serving for timing controlling a circuit portion in the peripheral circuit, the merge clock signal being defined as having a first signal period in which the external timing signal serves as a clock source and a second signal period without overlapping the first signal period, in which the internal clock signal serves as a clock source.

REFERENCES:
patent: 6567319 (2003-05-01), Sato et al.
patent: 6570814 (2003-05-01), Farmwald et al.
patent: 6715020 (2004-03-01), Farmwald et al.
patent: 10-302488 (1998-11-01), None

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