Non-volatile semiconductor memory device and electric device...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185110, C365S185170, C365S185250

Reexamination Certificate

active

06967874

ABSTRACT:
A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells disposed at the respective intersections of word lines and bit lines intersecting each other; a row decoder circuit for selectively driving a word line of the cell array; a sense amplifier circuit disposed in communication with the cell array for data reading and writing; and a controller for executing sequence control of data write and erase, wherein in a data erase cycle controlled by the controller to erase memory cells disposed along at least one selected word line of the cell array, an adjacent
on-selected word line which is non-selected and adjacent to the selected word line in non-selected words lines in the cell array is precharged to a first erase-inhibition voltage, while the remaining non-selected word lines are precharged to a second erase-inhibition.

REFERENCES:
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patent: 5511022 (1996-04-01), Yim et al.
patent: 6023423 (2000-02-01), Aritome
patent: 6144582 (2000-11-01), Atsumi et al.
patent: 6711058 (2004-03-01), Hirano
patent: 9-180482 (1997-07-01), None
patent: 10-188578 (1998-07-01), None

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