Non-volatile semiconductor memory device and data write...

Details Non-volatile semiconductor memory device and data write... Non-volatile semiconductor memory device and data write...

2003-08-08

2004-12-14

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185180, C365S185240

Reexamination Certificate

active

06831858

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device comprising a plurality of memory cells and a method for controlling data writing to the non-volatile semiconductor memory device.
2. Description of the Related Art
ETOX (EPROM Thin Oxide, Intel's registered trademark) flash memory is the most commonly used non-volatile semiconductor memory device.
FIG. 16
shows a memory cell
1600
contained in an ETOX flash memory. The memory cell
1600
comprises a semiconductor substrate
160
, a tunnel oxide film
163
, a floating gate
164
, an interlayer insulating film
165
, and a control gate
166
. In the semiconductor substrate
160
, a source region
161
and a drain region
162
are formed with a distance therebetween. The tunnel oxide film
163
, the floating gate
164
, the interlayer insulating film
165
, and the control gate
166
are laminated in this order over an end of the source region
161
, an end of the drain region
162
, and the semiconductor substrate
160
between the source region
161
and the drain region
162
.
The principle of operation of an ETOX flash memory will be described below.
Table 1 shows conditions for voltages applied to a memory cell in the modes of data writing, data erasing, and data reading of an ETOX flash memory.
TABLE 1
Control gate
Drain
Source
Substrate
Data write
9 V
5 V/0 V
0 V
0 V
mode
Data erase
−9 V 
Open
6 V
0 V
mode
Data read
5 V
1 V
0 V
0 V
mode
In data write (program) mode, a data writing voltage Vpp (e.g., 9 V) is applied to the control gate
166
. A reference voltage Vss (e.g., 0 V) is applied to the source region
161
and the semiconductor substrate
160
. A voltage of 5 V is applied to the drain region
162
. Note that a voltage of 0 V is applied to the drain region
162
of the memory cell
1600
when data writing is not performed.
A large current flows through the channel layer between the source region
161
and the drain region
162
. In this case, hot electrons are generated in the drain region
162
having a higher potential and then are injected into the floating gate
164
. As a result, the memory cell
1600
enters the data written state where the threshold voltage of the memory cell
1600
is increased.
FIG. 17
is a graph showing the distribution of the threshold voltages of memory cells contained in a two-value flash memory. In the graph, the horizontal axis represents the threshold voltage of a memory cell, while the vertical axis represents the number of memory cells.
Typically, when electrons are injected into the floating gate of a memory cell, the memory cell enters the data written (programmed) state. The data written (programmed) state is represented by Data “0”. When electrons are removed from the floating gate of a memory cell, the memory enters the data erased state. The data erased state is represented by Data “1”.
When the threshold voltage of a memory cell goes higher than or equal to a predetermined voltage value (e.g., 5 V), data writing (programming) is ended. When the threshold voltage of a memory cell goes lower than or equal to a predetermined voltage value (e.g., 3 V), data erasing is ended.
In data erase mode, a voltage Vnn (e.g., −9 V) is applied to the control gate
166
(Table 1) and a voltage Vpe (e.g., 6 V) is applied to the source region
161
(Table 1). Therefore, the drain region
162
is opened. As a result, electrons are removed from the floating gate
164
of the channel layer via the tunnel oxide film
163
in the source region
161
, thereby reducing the threshold voltage of the memory cell
1600
. The threshold voltage distribution of a memory cell in the data erase mode is the same as the threshold voltage distribution of a memory cell in the data erased state shown in FIG.
17
.
In data erase mode, a BTBT (Band To Band Tunneling) current flows between the source region
161
and the semiconductor substrate
160
. As the BTBT current is generated, hot holes and hot electrons are generated simultaneously. The hot electrons flow into the drain region
162
. The hot holes are attracted by the tunnel oxide film
163
and trapped into the tunnel oxide film
163
.
It is generally said that the phenomenon that hot holes are trapped by the tunnel oxide film
163
reduces the reliability of data holding in a memory cell.
In data read mode, a voltage of 1 V is applied to the drain region
162
(Table 1). A voltage of 5 V is applied to the control gate
166
(Table 1).
When a memory cell is in the data erased state (the threshold voltage is low), a current flows through the memory cell, so that the state of the memory cell is determined to be Data “1” (FIG.
17
). When a memory cell is in the data written (programmed) state (the threshold voltage is high), no current flows through the memory cell, so that the state of the memory cell is determined to be Data “0” (FIG.
17
).
A flash memory comprises a sense amplifier circuit. The sense amplifier circuit detects a current flowing through a memory cell, from which data is read, and a current flowing through a reference cell and compares the values of these currents to determine whether the memory cell is in the data erased state (the threshold voltage is low) or in the data written (programmed) state. The reference cell has a predetermined reference threshold voltage.
A method for determining data read from a memory cell using a sense amplifier circuit will be described.
FIG. 18
shows the configuration of a sense amplifier circuit. The sense amplifier circuit comprises an amplifier
181
. The amplifier
181
comprises a positive input terminal and a negative input terminal.
The positive input terminal of the amplifier
181
is connected to the drain terminal of an NMOS transistor
184
. The source terminal of the NMOS transistor
184
is connected to the drain terminal of the reference cell
186
. An inverter
182
is provided between the gate terminal and source terminal of the NMOS transistor
184
. The gate terminal of the NMOS transistor
184
is connected to the output terminal of the inverter
182
. The input terminal of the inverter
182
is connected to the source terminal of the NMOS transistor
184
. The gate terminal of the reference cell
186
is connected to a word line. A word line voltage VWL is applied to the word line. The source terminal of the reference cell
186
is connected to the earth (GND).
The negative input terminal of the amplifier
181
is connected to the drain terminal of the NMOS transistor
185
. The source terminal of the NMOS transistor
185
is connected to the drain terminal of a memory cell
187
contained in a main array. An inverter
183
is provided between the gate terminal and source terminal of the NMOS transistor
185
. The gate terminal of the NMOS transistor
185
is connected to the output terminal of the inverter
183
. The input terminal of the inverter
183
is connected to the source terminal of the NMOS transistor
185
. The gate terminal of the memory cell
187
is connected to a word line. A word line voltage VWL is applied to the word line. The source terminal of the memory cell
187
is connected to the earth (GND).
Typically, when data is read from the memory cell
187
contained in a flash memory, the sense amplifier circuit compares a current Im flowing through the memory cell
187
and a current Ir flowing through the reference cell
186
to determine whether the state of the memory cell
187
is Data “0” or Data “1” (FIG.
18
).
When the current Im flowing through the memory cell
187
is greater than the current Ir flowing through the reference cell
186
(Im>Ir), the sense amplifier circuit determines that the state of the memory cell
187
is Data “1” representing the data erased state. When the current Im flowing through the memory cell
187
is smaller than the current Ir flowing through the reference cell
186
(Im<Ir), the sense amplifier circuit determines that the state of the memory cell
187
is Data “0” representing the data written state.
In the case where th

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