Non-volatile semiconductor memory device and data programming me

Details Non-volatile semiconductor memory device and data programming me Non-volatile semiconductor memory device and data programming me

1994-08-26

1996-11-26

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, 36518501, G11C 700

Patent

active

055792600

ABSTRACT:
In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of "0" or "1" of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

REFERENCES:
patent: 4933904 (1990-06-01), Stewart
patent: 4953129 (1990-08-01), Kobayashi et al.
patent: 4962481 (1990-10-01), Choi et al.
patent: 5299162 (1994-03-01), Kim et al.
patent: 5369609 (1994-11-01), Wang et al.
patent: 5414658 (1995-05-01), Challa

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