Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-30
2003-01-28
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180
Reexamination Certificate
active
06512702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device (EEPROM) capable of electrically rewriting data and batch-erasing data in every block. More specifically, the invention relates to the improvement of a data erase sequence.
2. Description of the Related Background Art
A typical NAND type EEPROM has the function of selecting and batch-erasing one or more blocks of a memory cell array (see, e.g., Japanese Patent No. 2667617). Such a batch-erasable EEPROM has the function of carrying out an erase verify readout for determining whether a memory cell of an erased block is sufficiently erased, and erasing the selected block(s) again if the erase is insufficient. This function is automatically carried out by means of a sequencer provided in a chip.
Specifically, when data of an EEPROM of this type is erased, a user system inputs the address of a selected block, which includes a plurality of objects to be erased, and an erase executing command to an EEPROM chip. Thus, on the chip side, data erase is started, and thereafter, busy signals are outputted until a series of data erasing operations including a verify operation are completed. During this, the user system side is not accessible to the chip and is in a waiting state until the erasing operations are completed.
Specifically, the data erasing operations are carried out by, e.g., applying a boosted erase voltage to a p-type well, in which a memory array is formed, applying 0V to all of the word lines of the selected block, and allowing the word lines of the unselected blocks to be floating. At this time, in the memory cells of selected blocks, electrons of floating gates are emitted to the substrate side, so that data are batch-erased. In the unselected blocks, the potentials of the word lines are raised by capacitive coupling, so that data are not erased.
After a predetermined erase time elapses by an internal timer, the erasing operations are completed, and the erase voltage of the cell array is discharged. Thereafter, in order to carry out the verify operation, the operation for retrieving the selected block is carried out. That is, the operation for retrieving the erase selected block is repeated while incrementing the address, and only when the block selected during data erase is retrieved, the verify readout is carried out with respect to the selected block. After the verify readout, if it is determined that the erase is sufficient, the retrieving operation is continued until the address to be erased reaches the final address. When the address to be erased reaches the final address, all of the data erasing operations are completed. After the verify operation, if it is determined that the erase is insufficient, erase is carried out again, and the selected block retrieval and the verify are repeated again.
By the way, as the capacity of an EEPROM increases, a memory cell array is often divided into a plurality of cell array regions. The plurality of cell array regions are usually formed in different wells. Also in this case, data erase can be carried out over the plurality of cell array regions to select an optional block therefrom to batch-erase the selected block. However, in the above described conventional data erase sequence, there is a problem in that it takes a lot of time to carry out the retrieving operation for the erase verify. The retrieving operation is repeated until the address of an address register reaches the final address, and the address of the address register is incremented in order to carry out the verify operation for the selected and erased block. Specifically, when the memory cell array is divided into two cell array regions, and when each of the cell array regions has 1024 blocks, it is required to carry out 2048 retrieving operations in total.
The time required to carry out all of the data erasing operations viewed from the outside of the chip is the sum of the net erase time, in which erase pulses are applied, the time required to carry out the operation for retrieving the selected block, and the time required to carry out the verify readout. Since the time required to carry out one retrieving operation is about hundreds of ns, the time required to retrieve all of the blocks to be erased approximates 1 ms. Since the net time required to erase data is in the range of from 1 ms to 2 ms, the percentage of the time required to carry out the retrieving operations to the whole erase time reaches tens %. This problem becomes more serious as the capacity of the EEPROM further increases.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide an EEPROM capable of shortening the time required to retrieve a selected block for a verify operation after data erase, to shorten the time required to carry out the whole data erase.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a non-volatile semiconductor memory device includes:
a memory cell array divided into a plurality of cell array regions, each of which includes a plurality of blocks, each of the blocks having electrically rewritable non-volatile memory cells arranged therein;
a data erasing part for selecting one or more of the blocks of the memory cell array to batch-erase data in the selected block(s) as an erased block(s) to be erased;
an erase information holding part, provided in each of the blocks of the memory cell array, for holding erase information indicating whether the block is one of the erased block(s);
a retrieving part for sequentially reading the erase information, which is held by the erase information holding part in each of the plurality of cell array regions, for every one of the blocks to detect the erased block(s), the retrieving part reading the erase information at the same timing for every one of the blocks in each of the cell array regions when the retrieving part reads the erase information from the erase information holding part; and
an erase verify part for carrying out an erase verify for confirming an erased state of the memory cells with respect to the erased block(s), which are detected by the retrieving part, the erase verify part repeating a data erase operation with respect to the erased block(s) which are erased insufficiently, and the erase verify part carrying out the erase verify in parallel with respect to the erased block(s) which are detected on the basis of the erase information read at the same timing by the retrieving part.
According to another aspect of the invention, a non-volatile semiconductor memory device includes:
a memory cell array divided into a plurality of cell array regions, each of which includes a plurality of blocks, each of the blocks having electrically rewritable non-volatile memory cells arranged therein;
a data erasing part for selecting one or more of the blocks of the memory cell array to batch-erase data in the selected block(s) as an erased block(s) to be erased;
an erase information holding part, provided in each of the blocks of the memory cell array, for holding erase information indicating whether the block is one of the erased block(s);
a detecting part for reading the erase information, which is held by the erase information holding part in each of the plurality of cell array regions, to detect whether the erased block(s) exist in each of the cell array regions; and
an erase verify part for carrying out an erase verify for confirming an erased state of the memory cells with respect to the erased block(s) in the cell array regions in which the presence of the erased block(s) is detected by the detecting part, the erase verify being carried out with respect to the erased blocks by sequentially reading the erase information for every one of the blocks, and a data erase operation being repeated with respect to the erased block(s) which are erased insufficiently.
According to another aspect of the present invention, a non-volatile semiconductor memory device inc
Kanazawa Kazuhisa
Nakamura Hiroshi
Sakui Koji
Sugiura Yoshihisa
Yamamura Toshio
Banner & Witcoff , Ltd.
Ho Hoai
Kabushiki Kaisha Toshiba
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