Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-12-10

2004-05-25

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S233100, C365S189050, C365S201000, C365S226000, C365S228000

Reexamination Certificate

active

06741499

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Application No. 2001-376032, filed on Dec. 10, 2001, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor device.
2. Description of Related Art
A large scale semiconductor memory device is formed to contain redundant circuits for replacing defective cells with them. It's the same to an electrically erasable and programmable non-volatile semiconductor memory device (EEPROM). In a conventional redundant system, a redundant row cell array and a redundant column cell array are disposed in addition to a normal cell array, and a fuse circuit is disposed for storing defective addresses. Such the fuse circuit is typically formed by use of laser-programming type fuses.
A defective address is found in a wafer test, and programmed in the fuse circuit. After the fuse circuit programming, an input address is transferred to the fuse circuit and compared with the programmed defective addresses. If address matching is detected, decode circuits are controlled by the detected output to replace a defective cell array with a redundant cell array.
Fuse circuits are used for storing not only the above-described defective addresses, but also many kinds of initial set-up data (i.e., initializing data) that are used for determining memory operation conditions. Such initial set-up data include, for example, trimming data for adjusting internal voltages in corresponding to a process variation among wafers or chips, another trimming data for adjusting programming voltage, control parameters such as sequence loop numbers of program and/or erase sequence, and the like.
However, once the fuse circuit is programmed, it is impossible to reprogram the fuse circuit. Further, the wafer test for detecting defective addresses by use of a tester and laser-programming process for the fuse circuit are performed as different processes from each other. These processes can not be performed as one continuing step. Considering the above-described viewpoint, it has been provided to use such a system that non-volatile memory cells as similar to that of an EEPROM are used as an initial set-data storing circuit in place of the fuse circuit. By use of such the system, data programming may be performed more easily than the fuse circuit, and data reprogramming may also be performed.
However, if a cell array for storing defective addresses and the like is disposed at a different place from the normal cell array area, decode circuits and sense amp circuits are necessary for the respective cell arrays. Therefore, the circuit configuration becomes to be complicated, and the chip size becomes large. Additionally, in such a case that check and correct of the programmed data is required, operation control thereof is not easy.
In order to solve such the problem, the present inventors have already provided such a system that an initial set-up data region is defined in the normal cell array (see, Japanese Patent Application 2001-176290A). The initial set-up data stored in the initial set-up data region in the cell array are automatically read out after when the power supply is switched on by use of the same decoder and sense amp as used in normal data read mode, and then transferred to and held in the respective initial set-up data latch circuits. Hereinafter, the memory operation conditions are defined by the outputs of the initial set-up data latch circuits.
Bu use of such the system, the circuit configuration becomes simpler, and the chip size becomes smaller. Check and correct of the initial set-up data can also be performed easily. In this system, the period from power-on time to the initial set-up end becomes a waiting period while normal data read and normal data program are inhibited. Therefore, in such a case that the amount of the initial set-up data is large and/or verify operations are requested, it is necessary to shorten the above-described waiting period if possible.
Another reason why the waiting period becomes long is in such a fact that the initial set-up data are read out by an internal clock signal generated in the memory chip. While the internal clock is not adjusted by a trimming data that is prepared for canceling process variations, the clock cycle of the internal clock has a large variation. If the clock cycle is shifted to a long-cycle side, the waiting period will become long. Further, the read operation of the initial set-up data is performed as soon as power-on, the power supply voltage is not yet stable. This also leads the waiting period to be long.
SUMMARY OF THE INVENTION
A non-volatile semiconductor memory device is provided to include a memory cell array having electrically erasable and programmable non-volatile memory cells, a part of the memory cell array being defined as a initial set-up data region for storing a plurality of initial set-up data that define memory operation conditions, data latch circuits for holding the initial set-up data read out from the initial set-up data region, a controller for controlling data program and erase operations for the memory cell array, and a clock generator for generating a clock signal that is used to define an operation timing of the controller, wherein the controller is configured to perform such an initial set-up operation that sequentially reads out the plurality of initial set-up data stored in the initial set-up data region and transfers them to the respective data latch circuits on receipt of power-on or a command input, the initial set-up operation being so performed as to read out a clock cycle adjustment data within the plurality of initial set-up data stored in the initial set-up data region in the beginning, thereby adjusting a clock cycle of the clock signal output from the clock generator by use of the clock cycle adjustment data, and then read out the remaining initial set-up data by use of the adjusted clock signal.


REFERENCES:
patent: 4451903 (1984-05-01), Jordan
patent: 6052313 (2000-04-01), Atsumi et al.
patent: 6462985 (2002-10-01), Hosono et al.

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