Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-04-05
2003-11-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185140, C365S185160
Reexamination Certificate
active
06646916
ABSTRACT:
Japanese Patent Application No. 2001-115677, filed on Apr. 13, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device configured of memory cells each of which is provided with two non-volatile memory elements that are controlled by one word gate and two control gates.
A known type of non-volatile semiconductor device is a metal-oxide-nitride-oxide semiconductor or substrate (MONOS) wherein a gate insulation layer between the channel and the gate is formed of a multi-layer stack of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
This MONOS type of non-volatile semiconductor memory device was disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This document disclosed a MONOS flash memory cell provided with two non-volatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. In other words, each flash memory cell has two charge-trapping sites.
A plurality of MONOS flash memory cells of this configuration are arranged in both a row direction and a column direction, to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are required for driving this MONOS flash memory cell. It should be noted, however, that these lines can be connected in common if different control gates are set to the same potential during the driving of a large number of memory cells.
In this case, a flash memory operation is data erasure, programming, or reading. Data programming and reading is usually done for selected cells for eight or 16 bits simultaneously, but data erasure is simultaneously done over a much wider range.
In such a case, data disturbance becomes a cause of concern with this type of non-volatile memory. Data disturbance refers to the disturbance of data in non-selected cells, during programming or erasure done by repeating a programming or erasure state in which a high potential is applied even to cells within the non-selected sector region by the common wiring, during programming or erasure in which a high potential is applied to the control gate line and bit line of the selected cells.
To prevent such a situation, the configuration could be such that a select gate circuit is provided to ensure that the high potential is applied only to cells in the selected sector, whereas no high potential is applied to cells in non-selected sector.
With such a configuration, however, the select gate circuit takes up some surface area, preventing a high degree of integration of the memory cells. In addition, if a voltage drop occurs in the select gates, it is necessary to supply an increased voltage to allow for that voltage drop, in order to supply a high potential to cells in selected sectors during programming or erasure. As a result, low-voltage drive is impeded, making this unsuitable for equipment that demands a low power consumption, such as portable equipment in particular.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a non-volatile semiconductor memory device that enables a high degree of integration without requiring a selection gate circuit, while preventing any disturbance of data in cells in non-selected sectors during the programming or erasure of selected cells.
The present invention may also provide a non-volatile semiconductor device that prevents any voltage drop by making a selection gate circuit unnecessary, thus reducing the power consumption thereof.
According to one aspect of the present invention, there is provided a non-volatile semiconductor memory device has a memory cell array region in which are disposed a plurality of memory cells in both a column direction arid a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates. The non-volatile semiconductor memory device further provided with a control gate drive section which drives the first and second control gates of the memory cells within the memory cell array region.
The memory cell array region is divided in the row direction into a plurality of sector regions. Each of the sector regions has a plurality of memory cells disposed in each of columns arrayed in the column direction.
The control gate drive section has a plurality of control gate drivers each of which corresponds to one of the sector regions. Each of the control gate drivers is capable of setting a potential for the first and second control gates within the corresponding sector region, independently of other sector regions.
During the programming of selected cells within one sector region, this configuration makes it possible to ensure that the corresponding control gate driver applies the programming or erasure potential only to the control gates of the memory cells (selected cells and non-selected cells) within that sector region. Since other sector regions can be set to have a potential other than the programming or erasure potential by the corresponding control gate drivers, there is no disturbance of data in the cells within the non-selected sector regions. This also makes it possible to provide a high degree of integration of the memory cells, because this effect can be achieved without the use of a select gate circuit. Since there is also no voltage drop due to the select gate circuit, low-voltage drive is enabled, which is particularly advantageous for memory used in portable equipment.
When data is erased, one of the control gate drivers may be selected and supply a first high potential for erasure to all of the first and second control gates within the corresponding sector region, to erase data in a batch in each of the plurality of sector regions.
A plurality of control gate lines may be formed to extend in the column direction in each of the sector regions, and the control gate drive section may be connected directly to the control gate lines disposed in each of the sector regions, with no intervening gate circuit.
This ensures that no high potential is applied to non-selected cells within non-selected sector regions, even when the gate circuit that would increase the surface are a and generate a voltage drop has been removed.
In this case, the control gate lines may include: a plurality of main control gate lines connected directly to the control gate drive section; and a plurality of sub-control gate lines that connect the main control gate lines to the first and second control gates of the memory cells. These lines can be formed by metal wiring in different layers.
In this case, an even-numbered main control gate line in each of the sector regions may be connected to one of the sub-control gate lines to which the second control gates of the memory cells in an even-numbered column and the first control gates of the memory cells in an odd-numbered column are commonly connected. Similarly, an odd-numbered main control gate line in each of the sector regions may be connected to another one of the sub-control gate lines to which the second control gates of the memory cells in the odd-numbered column and the first control gates of the memory cells in the even-numbered column are commonly connected.
Moreover, if k main control gate lines are connected to each of the control gate drivers each of which corresponds to one of the sector regions, the memory blocks corresponding to I/O lines formed by a group of the memory cells connected to k sub-control gate lines are arranged in the row direction in each of the sector regions. In this case, a plurality of wires may be provided extending in the row direction. Each of the wires could connect one of the k main control gate lines to the corresponding one of the k sub-control gate lines.
The number of the memory-cells arranged in the row direction in each of the memory blocks could be 4. In such a case, k is set to 4 and four main control gate lines are connected to the control
Elms Richard
Hur Jung H.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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