Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-10-16
2003-09-16
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189011
Reexamination Certificate
active
06621740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor device, and more particularly, to a configuration for ensuring security to maintain the confidentiality of stored information.
2. Description of the Background Art
Non-volatile semiconductor memory devices such as a flash EEPROM (Electrically Erasable/Programmable Read Only Memory; hereinafter referred to as “flash memory”) have advantageous characteristics that data can be stored in a non-volatile manner and can be held without any power supply.
FIG. 18
schematically shows the entire configuration of a conventional flash memory. In
FIG. 18
, a flash memory
900
includes: a memory array
901
having a plurality of non-volatile memory cells arranged in a matrix of rows and columns; an X-decoder
902
for selecting a row of memory cells in memory array
901
in accordance with a received X-address; a Y-decoder
903
for generating a column selecting signal for selecting a column of memory cells in memory array
901
; a Y-gate
904
for connecting a selected column of memory array
901
to an internal data line in accordance with the column selecting signal received from Y-decoder
903
; and a data register
905
for temporarily storing write data in data writing. Data register
905
includes a register circuit provided corresponding to each of the columns of memory cells in memory array
901
, and stores write data applied via Y-gate
904
. Writing and write verification of data are carried out in accordance with the data stored in data register
905
.
Flash memory
900
further includes: a data input/output buffer
907
for externally inputting/outputting data via a data/address terminal group
906
; an address input buffer
908
for receiving an address signal applied via address/data terminal group
906
to generate internal address signals (X- and Y-address signals); and a control signal input buffer circuit
910
receiving control signals applied via a control terminal group
909
to generate internal control signals.
The control signals applied to control terminal group
909
include an output enable signal OE instructing reading of data, a chip enable signal CE instructing that flash memory
900
is selected, and a write enable signal WE designating data writing or the timing of command taking.
Control signal input buffer circuit
910
includes an OE buffer
910
a
receiving output enable signal OE, a CE buffer
910
b
receiving chip enable signal CE, a WE buffer
910
c
receiving write enable signal WE, and a buffer
910
d
receiving the other control signals. When chip enable signal CE is activated, flash memory
900
determines that the externally-applied control signals are valid and takes in currently applied data/address signal. An internal output enable signal from OE buffer
910
a
is applied to data input/output buffer
907
and to address input buffer
908
, and an internal chip enable signal from CE buffer
910
b
is also applied to data input/output buffer
907
and address input buffer
908
. When both output enable signal OE and chip enable signal CE are activated, data reading is carried out.
Flash memory
900
further includes: an X-address buffer
911
for buffering the internal address signal received from address input buffer
908
to generate an internal X-address signal to be supplied to X-decoder
902
; a write data input driver
912
buffering the write data received from data input/output buffer
907
and writing the data into data register
905
via Y-gate
904
in data writing; a read data output amplifier
913
for amplifying internal read data read out via Y-gate
904
and applying the amplified data to data input/output buffer
907
in data reading; a command control circuit
914
receiving the internal control signals from control signal input circuit
910
and the command from address input buffer
908
and determining a designated operation mode; a read/write/erasure control circuit
915
generating control signals required for the designated operation mode according to the operation mode instruction from command control circuit
914
; and a high voltage generating circuit
916
for generating a high voltage required for the write/erasure, under the control of read/write/erasure control circuit
915
.
For example, when the internal chip enable signal from CE buffer
910
b
is being activated, command control circuit
914
takes in a command from address input buffer
908
in response to the rise of the internal write enable signal from WE buffer
910
c
and decodes the command that is taken in. Read/write/erasure control circuit
915
is constituted by a processor such as a sequence controller, and generates control signals required for the operation designated by command control circuit
914
to control the operation of each circuit.
High voltage generating circuit
916
generates a high voltage to be required for write/erasure. The high voltage generated by high voltage generating circuit
916
is different depending on a configuration of the memory array, and portions that require such a voltage are supplied with the generated high voltage. To the memory cells and the substrate region, a high voltage is actually applied via X-decoder
902
, Y-decoder
904
and a source line decoder (not shown). Though
FIG. 18
shows that the high voltage from high voltage generating circuit
916
is applied to X-decoder
902
, the high voltage generated by high voltage generating circuit
916
may also be applied to the substrate region of memory array
901
(on a sector basis) or to a source line.
Read/write/erasure control circuit
915
further controls command control circuit
914
for the acceptance of a command in writing/erasing. Read/write/erasure control circuit
915
controls the operation of X-address buffer
911
to sequentially change an X-address in erasure verification mode and to select memory cells when a flash (collective) erasure is performed at the erasing operation, for example.
In memory array
901
, each of the non-volatile memory cells arranged in a matrix of rows and columns is generally constituted by a floating gate type transistor, and stores information depending on a threshold voltage of the floating gate type transistor.
FIG. 19
shows an example of a configuration of memory array
901
shown in FIG.
18
.
FIG. 19
exemplifies a configuration of an array portion of an AND-type flash memory.
In
FIG. 19
, memory cells MC are arranged in rows and columns, and an arrangement example is shown in
FIG. 19
, in which memory cells are arranged in 10 rows and 5 columns. A memory cell MC is constituted by one floating gate type field effect transistor MT. A bit line BL (BL
1
-BL
5
) is arranged corresponding to each column of memory cells MC, and a word line WL (WL
1
-WL
10
) is arranged corresponding to each row of memory cells MC. These memory cells MC are divided into a plurality of sectors in the column direction. One sector is constituted by memory units MU each including a predetermined number (five in
FIG. 19
) of memory cells MC in each column. The memory cells MC included in the same memory unit MU are connected in parallel between a sub bit line SBL and a sub source line SSL. Sub bit line SBL is connected to a corresponding bit line BL (BL
1
-BL
5
) via a drain-side sector selecting transistor SWD, whereas sub source line SSL is connected to a main source line MSL via a source-side sector selecting transistor SWS. Drain-side sector selecting transistor SWD is selectively rendered conductive in response to a sector selecting signal VD (VD
1
, VD
2
), whereas source-side sector selecting transistor SWS is selectively rendered conductive in response to a sector selecting signal VS (VS
1
, VS
2
). In the AND-type flash memory, data can be erased sector by sector, and hence fast re-writing of data can be realized.
A memory cell MC stores information depending on the threshold voltage of memory transistor MT.
FIG. 20
shows an example of the distribution of the threshold voltages of memory cells MC. In
FIG.
Dohi Yoshitsugu
Hosogane Akira
Le Thong
McDermott & Will & Emery
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