Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-01-09

2003-07-08

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030, C365S185210, C365S189011

Reexamination Certificate

active

06590809

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device storing 2-bit information per memory transistor.
2. Description of the Related Art
FIG. 1
shows an example of the configuration of a memory array of a conventional EEPROM (Electrically Erasable Programmable ROM). In the conventional EEPROM, as shown in
FIG. 1
, a unit memory cell is constructed by two transistors; a switch transistor and a memory transistor, and information of one bit is stored in the memory transistor. As for arrangement of bits, as shown in
FIG. 1
, bits are defined by sequentially assigning b
0
, b
1
, b
2
, . . . to memory cells.
FIG. 2
is a block diagram showing a one-chip microcomputer in which a CPU (Central Processor unit), a memory, and the like are mounted on a one chip. Blocks of a memory, a serial interface unit, and a parallel interface unit are connected to a CPU via an address bus and a data bus, and data is transmitted/received by using the address and data buses.
FIG. 3
is a block diagram more specifically showing the memory block in
FIG. 2
as a single memory. Also in the case of seeing the memory block as a single memory, data is read/written from/to the CPU and the like via the address and data buses.
SUMMARY OF THE INVENTION
A memory cell storing information of two bits into one memory transistor has been studied by some of the inventors of the present invention. This memory cell has applied for patent under Japanese Patent Application No. 2000-83246. In the memory cell, as shown in
FIG. 4
, by accumulating charged in localized trapping regions at both edges in the channel direction of a nitride film sandwiched by oxide films, storage of 2-bit information to a single memory transistor is realized. As shown in
FIGS. 5A and 5B
, to read/write 2-bit information from/to the memory cell, a reading/writing operation is performed on the memory cell twice while interchanging the source and the drain. At the time of the reading operation, electrons are injected to a source-side edge of the nitride film. Also, a transistor is made conductive and Vth is detected. Further, an erasing operation can be performed by tunneling out the electrons trapped in the nitride film in a lump from the gate or well side. Such a memory cell has an advantage that the cell area per bit can be reduced to ½ to ⅓ of that of a conventional cell.
The inventors herein have studied the configuration of a memory array using the two bits per cell memory.
FIG. 6
is a diagram showing the configuration of a memory array in the case of applying the idea of the configuration of the conventional memory array shown in FIG.
1
.
In
FIG. 6
, in order to read/write two-bit information from/to one memory cell, as shown in
FIGS. 5A and 5B
, the memory cell has to be accessed twice while interchanging the source and drain. In the case where this memory array is assembled in a memory block of a one-chip microcomputer shown in
FIG. 2
, for example, when the CPU reads information of one byte (b
0
to b
7
), in the memory array configuration of
FIG. 6
, the CPU reads b
0
, b
2
, b
4
, and b
6
in the first read cycle and reads b
1
, b
3
, b
5
, and b
7
in the second read cycle. Alternately, in the memory block, a reading operation is performed twice. After reading b
0
to b
7
, read data is transmitted to the CPU. During this period, the CPU waits until b
0
to b
7
become ready.
In any of the cases, the CPU needs read cycles twice as many as that of the EEPROM memory array shown in FIG.
1
. In the case of using the memory array shown in
FIG. 1
, since only one bit is stored in one memory transistor, one byte of b
0
to b
7
can be simultaneously read by one read cycle of the CPU.
Also in the case where a single memory device as shown in
FIG. 3
is read by the CPU, when the two-bits-per-cell memory array as shown in
FIG. 6
is used, in a manner similar to the above, twice the read cycles are necessary. Such a problem occurs not only in the reading operation but also in the writing operation.
An object of the invention is to solve the problem such that reading/writing cycles of a memory using a memory cell storing two bits per cell are twice as compared with the conventional technique and to provide a peripheral control circuit using a memory array configuration capable of reducing an area.
In order to achieve the object, bit arrangement is not defined by sequentially assigning addresses to memory cells but is defined so that information can be read/written simultaneously on a plurality of bytes unit basis according to a reading/writing method.
By arranging a plurality of unit memory arrays, information of a plurality of bytes can be read/written simultaneously.
As a memory array in which a plurality of memories are arranged, to further reduce the area, the memory array is constructed by commonly using the drain or source of a unit memory. A reading method and a circuit in an even-numbered address and those in an odd-number address are made different from each other.
In the reading circuit, high speed reading is achieved by not performing conventional-type precharging.
Further, according to the purpose, reading circuits are combined, thereby optimally using the reading circuits.
The above and other objects of the invention will become apparent by the following detailed description and the appended claims with reference to the attached drawings. In the attached drawings, the same reference numeral denotes the same or similar components.


REFERENCES:
patent: 5999445 (1999-12-01), Rolandi et al.
patent: 6178113 (2001-02-01), Gonzalez et al.
“Design of CMOS VLSI,” edited by Tetsuya Iizuka, 1989, p. 189.

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