Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-06-10

2003-08-26

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185330, C365S063000

Reexamination Certificate

active

06611459

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device improved in its limited applications.
2. Description of the Background Art
A flash memory capable of erasing an entire memory array at one time (i.e., in a flash) is one of the non-volatile semiconductor memory devices. Flash memories have NOR-type, new-NOR-type and DINOR-type memory cell transistor structures.
FIG. 24
illustrates a program (write) operation of a NOR-type memory cell transistor.
FIG. 25
illustrates an erase operation of the NOR-type memory cell transistor.
FIG. 26
illustrates a read operation of the NOR-type memory cell transistor. The memory cell transistor shown in
FIGS. 24 through 26
has an NMOS structure.
The NOR-type memory cell transistor shown in
FIGS. 24 through 26
includes a source main region
41
and a drain region
31
both selectively formed in a surface of a semiconductor substrate
11
. A source diffusion region
42
having an impurity concentration lower than that of the source main region
41
is formed around the source main region
41
. A floating gate electrode
24
is formed on a portion of the semiconductor substrate
11
lying between the source main region
41
and the drain region
31
, with a tunnel oxide film
13
disposed between the semiconductor substrate
11
and the floating gate electrode
24
. A control gate electrode
23
is formed on the floating gate electrode
24
, with an intergate oxide film
16
therebetween.
A source terminal P
1
, a drain terminal P
2
, a gate terminal P
3
and a substrate terminal P
4
are provided for setting the potential of the source main region
41
, the drain region
31
, the control gate electrode
23
and the semiconductor substrate
11
, respectively.
With such an arrangement, the program operation of the NOR-type memory cell transistor is performed by setting the source terminal P
1
at 0 V, the drain terminal P
2
at a positive high voltage HV, the gate terminal P
3
at the positive high voltage HV, and the substrate terminal P
4
at 0 V, as shown in FIG.
24
. The above settings cause electrons to be injected into the floating gate electrode
24
because of a channel hot electron phenomenon, whereby the program operation (or the operation of setting the NOR-type memory cell transistor at a high Vth (high threshold voltage)) is performed.
The erase operation of the NOR-type memory cell transistor is performed by setting the source terminal P
1
at the positive high voltage HV, rendering the drain terminal P
2
floating (or open), setting the gate terminal P
3
at 0 V or at a negative high voltage MHV, and setting the substrate terminal P
4
at 0 V, as shown in FIG.
25
. The above settings cause electrons to be extracted from the floating gate electrode
24
because of an FN (Fowler-Nordheim tunneling) phenomenon near an edge of the source main region
41
, whereby the erase operation (or the operation of setting the NOR-type memory cell transistor at a low Vth (low threshold voltage)) is performed.
The read operation of the NOR-type memory cell transistor is performed by setting the source terminal P
1
at 0 V, the drain terminal P
2
at a positive low voltage HLow, the gate terminal P
3
at a read voltage VR (where low Vth<VR<high Vth), and the substrate terminal P
4
at 0 V, as shown in FIG.
26
. The above settings allow detection of whether or not the memory cell transistor enters the on state to identify whether the threshold voltage is high Vth or low Vth, whereby the read operation is performed.
FIG. 27
is a graph showing a distribution of the threshold voltage Vth of the NOR-type memory cell transistor. As shown in
FIG. 27
, high Vth indicating “0” is distributed above 6.0 V, and low Vth indicating “1” is distributed between 1.5 V and 3.0 V. As a result, a threshold voltage window width &Dgr;Vth
1
between the high Vth distribution and the low Vth distribution is 2.5 V.
FIG. 28
illustrates a program operation of a new-NOR-type memory cell transistor which is one type of the NOR-type memory cell transistor.
FIG. 29
illustrates an erase operation of the new-NOR-type memory cell transistor.
FIG. 30
illustrates a read operation of the new-NOR-type memory cell transistor. The memory cell transistor shown in
FIGS. 28 through 30
has an NMOS structure.
The new-NOR-type memory cell transistor shown in
FIGS. 28 through 30
includes a source region
45
and the drain region
31
both selectively formed in the surface of the semiconductor substrate
11
. The floating gate electrode
24
is formed on a portion of the semiconductor substrate
11
lying between the source region
45
and the drain region
31
, with the tunnel oxide film
13
disposed between the semiconductor substrate
11
and the floating gate electrode
24
. The control gate electrode
23
is formed on the floating gate electrode
24
, with the intergate oxide film
16
therebetween.
The source terminal P
1
, the drain terminal P
2
, the gate terminal P
3
and the substrate terminal P
4
are provided for setting the potential of the source region
45
, the drain region
31
, the control gate electrode
23
and the semiconductor substrate
11
, respectively.
With such an arrangement, the program operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P
1
at 0 V, the drain terminal P
2
at the positive high voltage HV, the gate terminal P
3
at the positive high voltage HV, and the substrate terminal P
4
at 0 V, as shown in FIG.
28
. The above settings cause electrons to be injected into the floating gate electrode
24
because of the channel hot electron phenomenon, whereby the program operation is performed.
The erase operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P
1
at the positive high voltage HV, rendering the drain terminal P
2
floating (or open), setting the gate terminal P
3
at the negative high voltage MHV, and setting the substrate terminal P
4
at the positive high voltage HV, as shown in FIG.
29
. The above settings cause electrons to be extracted from the floating gate electrode
24
because of the FN phenomenon throughout the channel, whereby the erase operation is performed.
The read operation of the new-NOR-type memory cell transistor is performed by setting the source terminal P
1
at 0 V, the drain terminal P
2
at the positive low voltage HLow, the gate terminal P
3
at the read voltage VR (where low Vth<VR<high Vth), and the substrate terminal P
4
at 0 V, as shown in
FIG. 30
, in a similar manner to the NOR-type memory cell transistor.
FIG. 31
is a graph showing a distribution of the threshold voltage Vth of the new-NOR-type memory cell transistor. As shown in
FIG. 31
, high Vth indicating “0” is distributed above 6.0 V, and low Vth indicating “1” is distributed between 1.5 V and 3.0 V, as in the NOR-type memory cell transistor. As a result, a threshold voltage window width &Dgr;Vth
2
between the high Vth distribution and the low Vth distribution is 2.5 V.
FIG. 32
illustrates a program operation of a DINOR-type memory cell transistor.
FIG. 33
illustrates an erase operation of the DINOR-type memory cell transistor.
FIG. 34
illustrates a read operation of the DINOR-type memory cell transistor. The memory cell transistor shown in
FIGS. 32 through 34
has an NMOS structure.
The DINOR-type memory cell transistor shown in
FIGS. 32 through 34
includes a source region
43
and a drain main region
32
both selectively formed in the surface of the semiconductor substrate
11
. A drain diffusion region
33
having an impurity concentration lower than that of the drain main region
32
is formed around the drain main region
32
. The floating gate electrode
24
is formed on a portion of the semiconductor substrate
11
lying between the source region
43
and the drain main region
32
, with the tunnel oxide film
13
disposed between the semiconductor substrate
11
and the floating gate electrode
24
. The control gate electrode
23
is formed on

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