Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2011-06-21

2011-06-21

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180

Reexamination Certificate

active

07965555

ABSTRACT:
A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

REFERENCES:
patent: 6330189 (2001-12-01), Sakui et al.
patent: 7760550 (2010-07-01), Fayrushin et al.
patent: 2007/0279994 (2007-12-01), Mokhlesi et al.
patent: 2007/0279995 (2007-12-01), Mokhlesi et al.
patent: 2002-133888 (2002-05-01), None
U.S. Appl. No. 12/499,237, filed Jul. 8, 2009, Futatsuyama.

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