Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-06-21
2011-06-21
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S230060, C365S051000, C365S200000, C365S185170
Reexamination Certificate
active
07965552
ABSTRACT:
A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence.
REFERENCES:
patent: 5848009 (1998-12-01), Lee et al.
patent: 7388782 (2008-06-01), Tokiwa
patent: 7466600 (2008-12-01), Roohparvar
patent: 2001-273798 (2001-10-01), None
Shirakawa Masanobu
Tokiwa Naoya
Ho Hoai V
Kabushiki Kaisha Toshiba
Norman James G
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
LandOfFree
Non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2664713