Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2000-04-20

2001-02-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

06191978

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device capable of speeding up a determination of a reading voltage, thereby making operations of reading stored information faster.
2. Description of the Related Art
In semiconductor memory devices, acceleration of access time required for reading and writing stored information is a significant challenge in order to improve their performance. It is needless to say that a same goes for non-volatile semiconductor memory devices such as a flash memory or a like.
In recent years, there is a tendency that a structure of the non-volatile semiconductor device is scaled down to increase a storage capacity, which presents a problem of drain disturbance.
For example, in a case of the flash memory, since application of a high voltage to a drain of a scaled-down floating gate-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) constituting a memory cell becomes difficult, it is necessary to discriminate the memory cell (hereinafter may be also referred to as an “OFF-cell”) in a state where an electric charge has been injected into a floating gate by using a low voltage of, for example, about 0.5 V as a bias voltage to be applied to the memory cell causing a current not to flow from a memory cell (hereinafter may be also referred to as an “ON-cell”) in a state where the electric charge has been drawn from the floating gate, allowing the current to flow. It is, therefore, required that a small difference in voltages for reading stored information from the memory cell be reliably detected and time required for determination of an outputting state be shortened as much as possible in order to enable a high speed reading.
Circuit configurations and one example of operations of a conventional non-volatile semiconductor memory device will be hereinafter described.
FIG. 8
is a schematic circuit diagram showing an example of configurations of a reading circuit in the conventional non-volatile semiconductor memory device.
FIG. 9
is a graph for explaining operations of a feedback-type bias circuit.
FIG. 10
is a schematic block diagram of a reading timing generating circuit used for the conventional non-volatile semiconductor memory device.
FIG. 11
is a timing chart showing reading operations in the conventional non-volatile semiconductor memory device.
FIGS. 12A
,
12
B are diagrams explaining determination of an outputting state for reading in the conventional non-volatile semiconductor memory device.
As shown in
FIG. 8
, the reading circuit in the conventional non-volatile semiconductor memory device is chiefly composed of a memory cell M
mn
shown as a representative one selected from a memory cell array (not shown) by a bit line BL
m
and a word line WL
n
, a bit line decoder BDE
m
shown as a representative one used to select the bit line BL
m
, a feedback-type bias circuit
1
, a load circuit
2
, a pre-charging circuit
3
, a sense circuit (SA)
4
and a latch circuit
5
.
Also, as depicted in
FIG. 8
, the feedback-type bias circuit
1
has N-channel transistors
11
,
12
,
13
and
14
and P-channel transistors
15
and
16
. A drain of the N-channel transistor
11
is connected to the load circuit
2
and a connecting point between the N-channel transistor and the load circuit
2
is hereinafter called “node C”. A source of the N-channel transistor
11
is connected to the bit line decoder BDE
m
and a connecting point between them is hereafter called “node B”. A gate of the N-channel
11
is connected to a drain of the N-channel transistor
14
and a connecting point between them is hereafter called “node A”. A source of the P-channel transistor
15
is connected to a power source V
DD
, its drain is connected to a node A and its gate is connected to a line of a sense amplifier activating signal SAE. A source of the P-channel transistor
16
is connected to the power source V
DD
, its drain is connected to a drain of the N-channel transistor
12
and its gate is connected to a line of the sense amplifier activating signal SAE. A gate of the N-channel transistor
12
is connected to its drain and its source is connected to the node A. A drain of the N-channel transistor
13
is connected to the node A, its source is connected to a ground and its gate is connected to a line of the sense amplifier activating signal SAE. A drain of the N-channel transistor
14
is connected to the node A, its source is connected to the ground and its gate is connected to the node B.
The load circuit
2
has a P-channel transistor
21
and an N-channel transistor
22
. A source of the P-channel transistor
21
is connected to the power source V
DD
, its drain is connected to a drain of the N-channel transistor
22
and its gate is connected to a line of the sense amplifier activating signal SAE. A gate of the N-channel transistor
22
is connected to its drain and its source is connected to the node C. The pre-charging circuit
3
has a P-channel transistor
31
and an N-channel transistor
32
. A source of the P-channel transistor
31
is connected to the power source V
DD
, its drain is connected to a drain of the N-channel transistor
32
and its gate is connected to a line of a bit line pre-charging signal ATDP. A source of the N-channel transistor
32
is connected to the node B and its gate is connected to the node A.
The sense circuit
4
is composed of a comparison circuit used to compare a reference voltage V
REF
from a reference circuit (not shown) with an output voltage V
A
at the node C connected to the drain of the N-channel transistor
11
of the feedback-type bias circuit
1
and to produce a signal showing a result of comparison. The latch circuit
5
is composed of a circuit used to latch an output of the sense circuit
4
in response to a sense amplifier output latching signal LAT.
The feedback-type bias circuit
1
has a function to supply a predetermined bias voltage V
B
to the memory cell M
mn
. The load circuit
2
functions as a load by acting as a source of a constant current provided by the power source V
DD
to the feedback-type bias circuit
1
. The pre-charging circuit
3
is used to supply a pre-charging current to the bit line BL
m
when the bit line BL
m
is selected. The sense circuit
4
is adapted to judge whether the memory cell M
mn
is in the ON-cell state or in the OFF-cell state by comparing the reading output voltage V
A
from the feedback-type bias circuit
1
with the reference voltage V
REF
from the reference circuit (not shown). The latch circuit
5
is adapted to latch a signal showing a judging result from the sense circuit
4
and to generate output data. In the feedback-type bias circuit
1
, while reading is not performed, since the sense amplifier activating signal SAE is high and the P-channel transistors
15
and
16
are turned OFF and the N-channel transistor
13
is turned ON, a voltage V
F
at the node A is almost 0 (zero) volts and, since the N-channel transistor
11
is in an OFF state, the voltage V
B
of the feedback-type bias circuit is 0 (zero) volts. On the other hand, while the reading is being performed, since the sense amplifier activating signal SAE is low, the P-channel transistors
15
and
16
are turned ON and the N-channel transistor
13
is turned OFF and, since a current flowing from the power source V
DD
through a switch composed of the P-channel transistor
15
and a current flowing from the power source V
DD
through a switch composed of the P-channel transistor
16
and through a constant current source load composed of the N-channel transistor
12
flows into the N-channel transistor
14
, the voltage V
F
generated at the node A is supplied to the gate of the N-channel transistor
11
. Though this causes a current to flow through the N-channel transistor
11
and the predetermined bias voltage V
B
to be generated at the node B, since a line for the predetermined bias voltage V
B
is connected to the gate of the N-channel transistor
14
, a current flowing through the N-channel transi

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