Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1999-11-24

2001-09-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S185110, C365S185230, C365S185290

Reexamination Certificate

active

06295227

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device comprising a NAND cell (a memory cell string) wherein a plurality of electrically rewritable memory cells are connected in series.
2. Description of the Related Art
As an electrically rewritable EEPROM, a NAND cell type EEPROM is known. Each of memory cells of the NAND cell type EEPROM has a stacked transistor wherein a floating gate (a charge storage layer) and a control gate are stacked up on a semiconductor substrate via an insulator film. A plurality of memory cells are connected in series so that adjacent memory cells share a source/drain to constitute a NAND cell. Such NAND cells are arranged in the form of a matrix to form a memory cell array.
The drain on one end of the NAND cell arranged in the column direction of the memory cell array is commonly connected to a bit line via a selecting transistor, and the source on the other end of the NAND cell is connected to a common source line via a selecting transistor. The word lines of memory cell transistors and the gate electrodes of the selecting transistors are commonly connected in the row direction of the memory cell array as word lines (control gate lines) and selecting gate lines, respectively.
Such a NAND cell type EEPROM is known by, e.g., the following literatures (1) and (2).
(1) K. -D. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE J. Solid-State Circuits, Vol. 30, pp. 1149-1156, November 1995.
(2) Y. Iwata et al., “A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM”, IEEE J. Solid-State Circuits, Vol. 30, pp. 1157-1164, November 1995.
FIG. 18
shows a NAND cell block of a memory cell array of a NAND cell type EEPROM. A plurality of memory cells M are connected in series so that adjacent memory cells share their sources and drains to constitute a NAND cell. One end of the NAND cell is connected to a bit line BL via a selecting transistor S
1
, and the other end of the NAND cell is connected to a common grounding conductor via a selecting transistor S
2
. The control gates of the memory cells M arranged in the lateral direction of
FIG. 18
are commonly connected to a word line WL. Similarly, the gates of the selecting transistors S
1
, S
2
are commonly connected to selecting gate lines SSL, GSL. The range of the NAND cell driven by a word line constitutes a NAND cell block.
Usually, such NAND cell blocks are arranged in a direction of a bit line to constitute a memory cell array. Each of the NAND cell blocks serves as a unit for data erase to carry out a so-called batch erase. The memory cell string along a selected word line in the NAND cell block is called one page, which serves as a unit for data read and write.
For example, in the case of an n-channel memory cell transistor, the memory cell M causes a positive threshold state (E type state), in which electrons are injected into a floating gate, and a negative threshold state (D type state), in which the electrons in the floating gate are emitted, to correspond to binary values to store data. For example, the D type state is defined as a data “1” holding state (erase state), and the E type state is defined as a data “0” holding state (write state). In addition, an operation for shifting the threshold of a memory cell, which holds data “1”, in a positive direction to the data “0” holding state is defined as a “write operation”, and an operation for shifting the threshold of a memory cell, which holds data “0”, in a negative direction to the data “1” holding state is defined as an “erase operation”. Throughout the specification, the following descriptions are based on these definitions.
FIG. 19
shows the relationship between the potentials of the respective parts in data erase, read and write operations in a selected NAND cell block of a memory cell array. In the erase operation, all of the word lines of the selected NAND cell block are set at 0 V, and the selecting gate lines SSL, GSL and bit lines BL thereof are set in floating (F). In addition, a high positive erase voltage Vera (e.g., an erase pulse of 3 ms and 21 V) is applied to the p-type wells of memory cells. As a result, the erase voltage is applied to the selected block between the wells and word lines, so that electrons in the floating gate are emitted to the wells by the FN (Flower-Nordheim) tunnel current. Thus, the memory cells in the NAND cell block are in an erase state of “1”.
At this time, unselected NAND cell blocks are not under the influence of the erase pulse by the capacity coupling of the word lines and wells in the floating state. A coupling ratio is calculated from a capacity connected to a word line in a floating state. In fact, the capacity between a word line of a polysilicon and a p-well in a cell region controls the total capacity. The coupling ratio obtained by the observed result is large, about 0.9. This prevents the FN tunnel current from flowing. An erase verify (verification) is determined by whether the threshold voltages of all of the memory cells in the selected block become, e.g., below −1 V.
The data read operation is carried out by applying 0 V to a selected word line and a given read voltage Vread (a voltage necessary to cause a channel to conduct regardless of the threshold) to unselected word lines and a selecting gate line and by reading the variation in potential of a bit line BL due to the presence of continuity of the selected memory cell.
The data write operation is carried out by applying a high positive write voltage Vpgm to a selected word line, a pass voltage Vpass to unselected word lines, Vcc to a selecting gate line SSL on the bit line side, and Vss=0V to a selecting gate line GSL on the common source line side and by applying Vss to a bit line BL, to which “0” is to be written, and Vcc to a write inhibited bit line BL (i.e., a bit line BL to be held in an erase state of “1”). At this time, in the selected memory cell connected to the bit line, to which the Vss is applied, the channel potential is held to be the Vss, and a great electric field is applied between the control gate and the channel to cause electron injection from the channel to the floating gate due to the tunnel current. In other unselected memory cells, which are connected to the same bit line and to which the Vpass has been applied, sufficient electric field for write is not applied, so that no write operation is carried out.
In the memory cell along the bit line, to which the Vcc has been applied, the channel of the NAND cell is pre-charged to the Vcc or Vcc−Vth (Vth is the threshold voltage of the selecting transistor), so that the selecting transistor is cut off. Then, if the write voltage Vpgm and the pass voltage Vpass are applied to the control gate, the channel potential is raised by the capacity coupling of the channel of the NAND cell in the floating state with the control gate, to which the Vpgm or Vpass has been applied, so that electron injection does not occur.
As described above, electron injection is carried out only in the memory cell at the intersection of the bit line, to which the Vss has been applied, and the selected word line, to which the Vpgm has been applied, so that “0” is written. In the write inhibited memory cell in the selected block, the channel potential is determined by the capacity coupling of the word line with the channel as described above. Therefore, in order to sufficiently enhance the write inhibit potential, it is important to sufficiently carry out the initial charge of the channel and to increase the capacity coupling ratio between the word line and the channel.
The coupling ratio B between the word line and the channel is calculated by B=Cox/(Cox+Cj), wherein Cox is the sum of gate capacities between the word lines and the channels, and Cj is the sum of junction capacitance of the source and drain of the memory cell transistor. In addition, the channel capacity of the NAND cell is the total of the sum Cox of the gate ca

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