Static information storage and retrieval – Floating gate – Particular biasing
Patent
1990-07-03
1993-08-31
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
365184, G11C 1134
Patent
active
052414981
ABSTRACT:
There is a provided non-volatile semiconductor memory device including a memory cell including a source, a drain, a floating gate, and a control gate. To read out data from the memory cell, a voltage of not more than 2 V, obtained by decreasing an external power source voltage, is applied to the drain of the memory cell. Various constants of the memory cell are set so as to control an ON current to be not more than 300 .mu.A when the memory cell is placed in an ON state while a threshold voltage of the memory cell is low.
REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky
patent: 4879689 (1989-11-01), Atsumi
patent: 4930105 (1990-05-01), Matsumoto
patent: 5010520 (1991-04-01), Minagawa
patent: 5095461 (1992-03-01), Miyakawa
Maruyama, T., "Wide Operating Voltage Range and Low Power Consumption EEPROM Structure for Consumer Oriented ASIC Application", IEEE 1988 Custom IC Conference, pp. 4.1.1-4.1.4, N.Y., May 16-18, 1988.
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
Zarahian A.
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