Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1980-05-20

1983-05-24

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 54, 357 59, 357 23, 365184, H01L 2702, H01L 2978, H01L 2934, H01L 2904

Patent

active

043853080

ABSTRACT:
A silicon nitride layer and a memory gate electrode are successively formed over a portion of a principal surface of a semiconductor substrate between drain and source regions formed therein and adjacent to the drain region via a thin silicon dioxide layer. A portion of the substrate principal surface, to which the source region is contiguous, is covered by a thick silicon dioxide layer, and a selection gate electrode is buried in the thick silicon dioxide layer. This two-input gate transistor construction constitutes a memory cell.

REFERENCES:
patent: 4090257 (1978-05-01), Williams
patent: 4112507 (1978-09-01), White et al.
patent: 4122544 (1978-10-01), McElroy
Yatsuda et al., "N-channel Si-gate MNOS Device for High Speed EAROM", Proc. 10th Conf. Solid State Devices, Tokyo, (1978); Japanese J. Applied Physics, vol. 18, (1979), Suppl. 18-1, pp. 21-26.
Dill et al., "A New MNOS Charge Storage Effect", Solid-State Electronics, vol. 12, (1969), pp. 981-987.
Tickle et al., "Electrically Alterable Non-Volatile Memory Technology", 1972 Wescon Technical Papers, Session 4, 4/2, pp. 1-8.

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2148075