Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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3651852, 36518523, 365200, G11C 1606

Patent

active

060785225

ABSTRACT:
A non-volatile memory device of the present invention comprises a memory cell array having a plurality of cells, a plurality of dummy bit lines, a plurality of dummy word lines. At least one of the dummy bit lines includes a bulk tapping for applying bulk voltage. Here, P.sup.+ impurity is implanted into the dummy bit lines. With this improved memory structure, a device layout area can be reduced and an increase in bulk voltage resulting from hot carriers can be suppressed.

REFERENCES:
patent: 4982364 (1991-01-01), Iwahashi
patent: 5214604 (1993-05-01), Kato
patent: 5463587 (1995-10-01), Maruyama
patent: 5822248 (1998-10-01), Satori et al.
patent: 5917768 (1999-06-01), Pascucci

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