Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1998-07-21

1999-11-16

Phan, Trong Q.

Static information storage and retrieval

Floating gate

Multiple values

36518518, 36518521, G11C 1604

Patent

active

059869305

ABSTRACT:
A word line is connected to a control gate of memory cell transistor, and a bit line and a source line are connected to a drain and a source of the memory cell transistor, respectively. A write clock having a certain crest value is applied to the source line, and an earth potential or a power supply potential is applied to the bit line in response to a read clock having a phase which is opposite to that of the write clock. A row selection clock which synchronizes with the write clock and a crest value of which is de-escalated is applied to the word line.

REFERENCES:
patent: 5818759 (1998-10-01), Kobayashi
patent: 5889699 (1999-03-01), Takano
Bauer, et al. "A Multilevel-Cell 32Mb Flash Memory," 1995 IEEE International Solid-State Circuits Conference, Session 7, Paper TA 7.7, pp. 132-133. ISBN 0-7803-2495-1/95.

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