Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1991-11-20

1994-02-01

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36523003, 36523006, 365900, 365195, G11C 1134

Patent

active

052837580

ABSTRACT:
A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

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Esquivel, J. et al., "High Density Contactless, Self Aligned EPROM Cell Array Technology," IEEE, IEDM 86 (1986), pp. 593-596.
Mitchell, A. et al., "A New Self-Aligned Planar Array Cell for Ultra High Density EPROMs," IEEE, IEDM 87 (1987), pp. 548-551.

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