Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2006-09-20

2008-09-02

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185200, C365S185220

Reexamination Certificate

active

07420844

ABSTRACT:
A memory cell array with a group of memory cells capable of retaining two-bit information. Each memory cell has a pair of transistors having charge storage regions, mutually connected gates, and mutually connected sources. Word lines are provided to the gates of the transistors. Bit lines are provided to the sources and drains of the transistors. A pair of the bit lines respectively connected to the drains of a pair of transistors included in a memory cell are connected to a comparison input terminal of the differential detector. An information retained in the memory cell is read based on a comparison result of current amounts inputted to the differential detector via the pair of bit lines obtained by the differential detector in a state where memory cell currents are simultaneously and independently supplied to the pair of transistors.

REFERENCES:
patent: 6411549 (2002-06-01), Pathak et al.
patent: 6480418 (2002-11-01), Tanaka et al.
patent: 6650568 (2003-11-01), Iijima
patent: 6807101 (2004-10-01), Ooishi et al.
patent: 6-268180 (1994-09-01), None

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