Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185030, C365S185110, C365S185200, C365S189090

Reexamination Certificate

active

07016232

ABSTRACT:
A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.

REFERENCES:
patent: 5351212 (1994-09-01), Hashimoto
patent: 5673223 (1997-09-01), Park
patent: 6122188 (2000-09-01), Kim et al.
patent: 6191979 (2001-02-01), Uekubo
patent: 10-050079 (1998-02-01), None
patent: 2000-268593 (2000-09-01), None
patent: 2001-36385 (2003-01-01), None
English language Abstract of Japanese Patent Publication No. 10-050079.
English language Abstract of Japanese Patent Publication No. 2000-268593.
English language Abstract of Korean Patent Publication No. 2001-36385 (2003-01608).

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