Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-12-10

2004-06-01

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185290

Reexamination Certificate

active

06744670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device in which characteristics of a memory cell changes with increase in the number of times of data rewriting. More particularly, the present invention relates to a configuration for performing a data rewriting operation in a non-volatile semiconductor memory device.
2. Description of the Background Art
In a non-volatile semiconductor memory device, writing (programming) or erasure is performed by injecting or ejecting electric charges to or from a floating gate or silicon nitride layer (Si
x
N
y
), which is electrically insulated, and provided between a word line (control gate) and a semiconductor substrate, to change a threshold voltage of a memory cell transistor.
By changing an electric charge quantity accumulated in a floating gate or a silicon nitride layer, a threshold voltage of a memory cell continuously changes. Therefore, by setting the number of segmented regions of the threshold voltage from conventional two regions to four or eight regions, 2-bit data or 3-bit data can be stored in one memory cell. Such a memory storing data of multiple bits in one memory cell (memory cell transistor) is generally called a multi-valued memory.
FIG. 32
indicates a distribution of threshold voltages of a multi-valued memory. In
FIG. 32
, the threshold voltage region is divided into four regions by read voltages VRW
0
, VRW
1
and VRW
2
and 4-valued or 4-level data (2-bit data) is stored in one bit memory cell.
A read voltage represents a voltage applied to the control gate of a selected memory in reading data stored in the memory cell.
In
FIG. 32
, the abscissa reads values of a threshold voltage of a memory cell transistor, and the ordinate indicates the number of bits. In such 4-valued memory, 2-bit data of “11”, “10”, “00” or “01” is stored in one memory cell. In order to perform correct reading/writing of data to/from the memory cell, restriction is imposed on distribution region of threshold voltages of memory cell transistors corresponding to the respective storage data. A threshold voltage of a memory cell transistor storing data “11” is defined to lie between a write verify voltage VWV
0
and an upper foot verify voltage VOP
0
. A threshold voltage of a memory cell transistor storing data “10” is defined to lie between a write verify voltage VWV
1
and an upper foot verify voltage VOP
1
.
A threshold voltage of a memory cell transistor storing data “00” is defined to lie between a write verify voltage VWV
2
and an upper foot verify voltage VOP
2
. The lower limit of the threshold voltage of the memory cell transistor storing data “01” is defined by a write verify voltage VWV
3
.
Accordingly, a threshold voltage of a memory cell transistor storing data “11” lies in the lowest threshold voltage region and a threshold voltage of the memory cell transistor storing data “01” lies in the highest threshold voltage region.
FIG. 33
is a sectional diagram showing an example of a structure of a non-volatile memory cell. In
FIG. 33
, the memory cell includes: impurity regions S and D formed, spaced from each other, at a surface of a semiconductor substrate region SUB; a floating gate FG formed above a surface of a substrate region between impurity regions S and D with an insulating film not shown interposed in between; and a control gate CG formed in an upper layer above floating gate FG with an interlayer insulating film interposing in between.
Control gate CG is formed being integrated with a word line. Impurity regions S and D serve as source and drain regions, respectively. Floating gate FG is electrically isolated from the surroundings and accumulates electric charges according to storage data.
The non-volatile memory cell is constituted of one stacked gate field effect transistor.
In data reading, read voltages VRW
0
, VRW
1
and VRW
2
are applied in a prescribed sequence to control gate CG. Source region S is set to ground voltage level and drain region D is supplied with a prescribed read voltage (for example, 2.0 V). When a threshold voltage of the memory cell is lower than a read voltage applied to control gate CG, a channel is formed between the source and drain regions in the memory cell to cause a current to flow from the drain region to the source region.
The drain region D is connected to a data line generally called a bit line and discrimination on stored data is made according to whether or not a current flows through the bit line. In data reading, for example, read voltages VRW
0
to VRW
2
are sequentially applied in a prescribed sequence. When read voltages VRW
0
to VRW
2
are applied, it is determined whether or not a current flow through a bit line and storage data in a memory cell is identified according a result of determination.
If no current flows through a memory cell transistor even when any of read voltages VRW
1
and VRW
2
is applied, it is determined that data “01” is stored in the memory cell. On the other hand, if no current flows when read voltage VRW
1
is applied, while a current flows when read voltage VRW
2
is applied, it is determined that data “00” is stored in the memory cell.
If a current flows through a bit line when read voltage VRW
0
is applied, while no current flows when each of read voltages VRW
1
and VRW
2
is applied, it is determined that data “11” is stored in the memory cell.
2-bit data is generated according to the results of determination and read out externally.
In data writing (programming) and erasing, in order to verify whether or not the writing/erasing is correctly performed, a verify voltage is applied to the control gate of the memory cell. In
FIG. 33
, there are also shown both of a control gate voltage and a bit line voltage applied in the verifying operation. A voltage in a range from 1.0 V to 6.0 V is applied to the control gate according to an operating mode and a voltage in the range from 0.5 V to 2.0 V is applied to the bit line (drain region D) according to an operating mode.
In a non-volatile semiconductor memory device, writing/erasing is implemented by moving electric charges through an insulating film immediately below a floating gate to change the electric charge quantity of the floating gate. Write (programming) characteristics or erasure characteristics of such a memory cell single is greatly varied by an influence of a film quality of the insulating film below the floating gate. Therefore, if a one shot writing pulse is generated in accordance with an externally applied write instructing signal as is done in a dynamic random access memory (DRAM) or a static random access memory (SRAM), writing and erasure cannot be performed such that threshold voltage of a memory cell falls within a prescribed range with sufficient correctness.
Therefore, it is needed to control a threshold voltage of a memory cell using an internal controller. As an example of control of a threshold voltage, a case is considered in which as shown in
FIG. 34
, electrons e are injected to floating gate FG from semiconductor substrate region SUB through Fowler-Nordheim (FN) tunneling phenomenon, thereby raising a threshold voltage of a memory cell transistor. Here, an operation of raising a threshold voltage of a memory cell is defined as writing.
In writing, a voltage in the range from 15 to 25 V is applied to control gate CG and source region S and drain region D is maintained at ground voltage level. In this state, a high electric field is applied between substrate region SUB and control gate CG to cause a FN tunneling phenomenon. Accordingly, electrons, e, flow through the insulating film between floating gate FG and substrate region SUB and are accumulated in floating gate FG and to raise the threshold voltage of the memory cell transistor.
Now, a case is considered in which a write pulse with a prescribed constant width at a prescribed constant voltage level is applied to control gate CG. In this case, as shown in
FIG. 35
, due to dif

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