Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2003-10-24

2004-11-02

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080, C365S185120, C365S185170

Reexamination Certificate

active

06813214

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to non-volatile semiconductor memory devices and, more specifically, to a method of sensing data stored in a memory cell of a flash memory device.
BACKGROUND OF THE INVENTION
A semiconductor memory device can be roughly classified as either a volatile semiconductor memory device or a non-volatile semiconductor memory device. Volatile semiconductor memory devices can be classified as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices. Volatile semiconductor memory devices have rapid read/write speeds but, unfortunately, the contents stored therein disappear when external power is cut off.
Non-volatile semiconductor memory devices can be classified as mask read-only memory (MROM) devices, programmable read-only memory (PROM) devices, erasable programmable read-only memory (EPROM) devices, or electrically erasable programmable read-only memory (EEPROM) devices. Non-volatile semiconductor memory devices hold their contents even when external power supply thereto is interrupted. Non-volatile semiconductor memory devices are therefore used to store contents that must be maintained even in the event of power loss.
In MROM, PROM, and EPROM devices, however, it is inconvenient to erase and write data, and general users therefore have difficulty updating the stored contents therein. Data stored in EEPROM devices, on the other hand, can be electrically programmed and erased quickly, and the use of these devices has therefore become popular in auxiliary memory and system programming devices that require continuous updating of contents. Furthermore, large-volume auxiliary memory devices typically use flash EEPROM devices because they have a higher integration density than conventional EEPROM devices. Among the various types of flash EEPROM devices, the integration density of NAND-type devices is generally higher than NOR- and AND-type devices.
A flash EEPROM device includes memory cells, each of which includes a floating gate transistor having a source, a drain, a floating gate, and a control gate. A memory cell in a NAND-type flash EEPROM device is electrically erased and programmed using Fowler-Nordheim (F-N) tunneling current. Various methods for erasing and programming NAND-type flash EEPROM devices are disclosed in U.S. Pat. No. 5,473,563, entitled “Nonvolatile Semiconductor Memory”, and in U.S. Pat. No. 5,696,717, entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability”, the disclosures of which are incorporated herein by reference.
In general, an erased memory cell (ON cell) stores data of a logic “1”. When a read voltage of 0V is applied to a word line coupled with the erased memory cell, current flows through the ON cell. A programmed memory cell (OFF cell) stores data of a logic “0”. When a read voltage of 0V is applied to a word line coupled with the programmed memory cell, no current flows through the OFF cell.
FIG. 1
is a schematic circuit diagram of a conventional non-volatile semiconductor memory device, according to the prior art. As illustrated in
FIG. 1
, bit lines BL
1
to BL
4
are arranged in communication with a memory cell array
10
. For clarity of description, only four bit lines BL
1
to BL
4
, and their related page buffers, are illustrated in FIG.
1
. The bit lines BL
1
to BL
4
are arranged in pairs BL
1
and BL
2
, BL
3
and BL
4
with each bit line pair connected to a corresponding sense node SO
1
, SO
2
through a respective bit line bias and select section
12
_O,
12
_E of the page buffer. A corresponding precharge section and a sense and latch section
14
_O,
14
_E is also connected to a respective one of the sense nodes SO
1
, SO
2
.
More specifically, an odd bit line bias and select section
12
_O selects a bit line of the first bit line pair BL
1
and BL
2
. An even bit line bias and select section
12
_E selects a bit line of the second bit line pair BL
3
and BL
4
. Each of the bit line bias and select sections
12
_O and
12
_E includes four NMOS transistors M
1
to M
4
, connected as illustrated. Selected bit lines are connected with corresponding sense nodes SO
1
and SO
2
, and unselected bit lines are fixed at a predetermined voltage (e.g., 0V). The precharge section of each page buffer includes a PMOS transistor M
6
. Each of the sense and latch sections
14
_O,
14
_E includes three NMOS transistors M
5
, M
7
, M
8
and a latch formed from two inverters INV
1
, INV
2
.
FIG. 2
is a timing diagram illustrating an operation of one of the page buffers of the conventional memory device of FIG.
1
. Referring to
FIGS. 1 and 2
, odd-numbered bit lines BL
1
, BL
3
and even-numbered bit lines BL
2
, BL
4
are selected by different page addresses, and a read operation is carried out in a page unit. When memory cells connected to bit lines of an even-numbered page address are accessed, memory cells connected to bit lines of an odd-numbered page address are shielded (and vice-versa).
Shielding unselected bit lines is done to prevent parasitic coupling capacitance between adjacent bit lines, which increases as a bit line pitch is reduced. If bit lines adjacent to selected bit lines are not shielded, then when a bit line connected to an ON cell is discharged, a voltage on a bit line connected to an OFF cell that is being floated may be coupled down together with the ON cell. When this happens, the OFF cell may be improperly recognized as an ON cell, thereby resulting in a read error.
Assuming, for example, that the even-numbered bit lines BL
2
, BL
4
are selected based on an even-numbered page address, the odd-numbered bit lines BL
1
, BL
3
are shielded by applying a ground voltage (0V) through the NMOS transistors M
1
. In this case, during a precharge period, a power supply voltage Vcc is supplied to the sense nodes SO
1
, SO
2
through the PMOS transistors M
6
. The PMOS transistors M
6
each have a gate that receives a precharge control signal nSOSHLD. At this time, the selected bit lines BL
2
, BL
4
are precharged with a precharge voltage Vpre through the fourth NMOS transistors M
4
, which are controlled by an even bias control signal BLBIAS_E. Unselected bit lines BL
1
, BL
3
are floated because the third NMOS transistors M
3
are turned off by an odd bias control signal BLBIAS_O.
After the selected bit lines BL
2
, BL
4
are charged up to the precharge voltage Vpre, a voltage on the even bias control signal BLBIAS_E is changed from the precharge voltage Vpre to a ground voltage GND, so that the fourth NMOS transistor M
4
of each bias and select section is turned off. The even bit lines BL
2
, BL
4
are then floated, while the sense nodes SO
1
, SO
2
are maintained at a high voltage level Vcc. When the selected bit lines BL
2
, BL
4
are floated, voltages of those bit lines BL
2
, BL
4
vary depending on states of corresponding cell transistors.
For example, assuming that an ON cell is connected to the second bit line BL
2
and an OFF cell is connected to the fourth bit line BL
4
, the second bit line BL
2
voltage is gradually reduced as cell current flows through the ON cell. The fourth bit line BL
4
voltage, however, is maintained at the precharge voltage Vpre because the corresponding OFF cell prevents current flow. During this “bit line develop period,” since the precharge control signal nSOSHLD is at a low level, each PMOS transistor M
6
becomes active, and each sense node SO
1
, SO
2
is thereby maintained at a high voltage level Vcc.
After voltages of the selected bit lines BL
2
, BL
4
have been developed, the even bias control signal BLBIAS_E has a sense voltage level Vsen that is lower than the precharge voltage level Vpre. This causes the fourth NMOS transistor M
4
, coupled with the second bit line (corresponding to an ON cell), to be turned on. The fifth NMOS transistor M
5
, coupled with the fourth bit line (corresponding to an OFF cell), is turned off.
Before a voltage of the even bias control signal BLBIAS_E is increased up to the sense voltage

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