Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-11-21

2004-07-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185330, C365S189050

Reexamination Certificate

active

06760256

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-358327, filed Nov. 22, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and more particularly to a non-volatile memory (Electrically Erasable Programmable ROM (Read Only Memory)) such as a NAND type flash memory in which data can be electrically rewritten.
2. Description of the Related Art
Conventionally, in a system containing a processor, an instruction which the processor first receives is output from a non-volatile memory such as a mask ROM or flash ROM. In a non-volatile memory which can output data according to the input state of address pins, the processor is only required to input the address to the non-volatile memory at the power supply turn-ON (startup) time. Particularly, in a NAND type flash memory used as the non-volatile memory, for example, an address area on the memory is specified and a plurality of data items are simultaneously reads out from the specified address area. Then, the plurality of readout data items are serially output in response to clock input of a read enable signal (/RE). In this case, “/” indicates an inverted signal (bar) of the corresponding signal for convenience.
FIG. 13
shows a case wherein the NAND type flash memory with the above configuration is used for startup (booting) of the system, for example. When the power supply of the system is turned ON, for example, a processor (not shown) supplies a startup (readout) control signal to a row address decoder
102
and data register
103
. When the readout control signal is supplied, data items in a preset address area (in this example, from page “0”) on a cell array
101
which is previously determined as a set value of the memory are read out to the data register
103
. The data items read out to the data register
103
are supplied to an input/output (I/O) buffer
104
and then output to the exterior according to clock input of a read enable signal /RE.
As the memory, a preset memory area corresponding to a plurality of successive addresses starting from the “0” address on the cell array
101
is defined as a data area to store system booting data. The memory is so designed that data items in the data area will be successively output in response to an external clock (read enable signal /RE).
However, the NAND type flash memory is normally used as a file storing memory (file memory). Therefore, it is not always preferable to store system booting data in an area corresponding to the “0” address on the cell array
101
. This is because there is a possibility that the data area for the system booting data and a data area (file management data storage area) to store file management data of the file memory will conflict with each other.
As described above, in the prior art, the NAND type flash memory can be used to boot the system, but in this case, there occurs a problem that the data area for the system booting data and a file management data storage area may conflict with each other.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising a non-volatile memory element group having a second storage area to store storage addresses of a first storage area which stores booting data, a detecting circuit which detects turn-ON of a power supply, a register to which the storage address stored in the second storage area is read out and transferred from the non-volatile memory element group when the detecting circuit detects turn-ON of the power supply, and a control circuit which performs a control operation to output booting data stored in the first storage area and corresponding to the storage address transferred to the register when an initialization operation performed at the power supply turn-ON time is terminated.


REFERENCES:
patent: 5379262 (1995-01-01), Okamoto et al.
patent: 6058048 (2000-05-01), Kwon
patent: 6462985 (2002-10-01), Hosono et al.
patent: 6646930 (2003-11-01), Takeuchi et al.
U.S. patent application Ser. No. 09/731,910, Hosono et al., filed Oct. 8, 2002.

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