Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-08-29

2004-07-27

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180

Reexamination Certificate

active

06768674

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a flash memory device with NOR-type memory cells.
BACKGROUND OF THE INVENTION
In speed of program and read operations, a NOR-type flash memory is far superior to electrically programmable and erasable non-volatile semiconductor memory device. Therefore, the NOR-type flash memory has been garnering warm response from users that require faster operation speed.
FIG. 1
shows a construction of a flash EEPROM cell. An N-type source region
3
and an N-type drain region
4
are formed on a P-type substrate or a bulk region
2
with a channel region interposed therebetween. A floating gate
6
, which is insulated by an insulating layer
5
of 100 Å or less, is formed on the P-type channel region. A control gate
8
, which is insulated by another insulating layer
7
, is formed on the floating gate
6
.
Channel hot electrons are injected into a floating gate from a channel region adjacent to a drain region, programming an EEPROM cell. The hot electron injection is carried out by grounding a source region and a P-type bulk region, applying a high voltage (e.g., +10V) to a control gate, and applying a voltage (e.g., 5V-6V) fitted for creation of hot electrons to the drain region
4
. If negative charges (injected hot electrons) are sufficiently accumulated to a floating gate, the floating gate has a negative potential, boosting up a threshold voltage in a sequential read operation. The reading operation is carried out by applying a suitable voltage (e.g., 1V) to a drain region, applying an optimum voltage (to distinguish an erased cell from a programmed cell) of 4.5V to the control gate, and applying a voltage of 0V to a source region and the P-type substrate. A threshold voltage distribution of the programmed cell generally has a range of 6V-7V, as shown in FIG.
2
. In the P-type substrate that is electrically separated from a floating gate by an insulating layer, a channel is not created. Accordingly, the memory cell is read out as logic “OFF state”.
F-N (Fowler-Nordheim) tunneling is made from a floating gate to a bulk (P-type substrate), erasing the EEPROM cell. A conventional tunneling manner is performed by applying a negative high voltage (e.g., −10V) to an electrode of the control gate and applying a suitable positive voltage (e.g., +5V) to the bulk region. In this case, the drain region holds a high impedance state or a floating state in order to maximize an erase effect. Due to such a manner, a strong electric field is created between the control gate and the bulk region. The F-N tunneling is made then, discharging negative charges in the floating gate to the source (or bulk). Generally, when an electric field of 6-7 MV/cm is created across an insulating layer, the F-N tunneling is made. A thin insulating layer of 100 Å or less is formed between the floating gate and bulk region, making the F-N tunneling. A threshold voltage distribution of the erased cell generally has a voltage range of 1V-3V, as shown in FIG.
2
. In the reading operation, a channel is created in the P-type substrate that is electrically separated from a floating gate by an insulating layer. Accordingly, the memory cell is read out as logic “ON state”.
When a memory cell array is constructed using the EEPROM cells, bulk regions of the cells are coupled to each other in order to achieve high integration. This causes a plurality of EEPROM cells sharing a bulk to be erased at the same time in the erasing operation. In this case, a region being an elementary unit of erasure is called a “block” or a “sector”. Voltages each being applied to a terminal in reading and erasing operations is illustrated in the following [TABLE 1]. And, a distribution of cell threshold voltages after programming and erasing operations is shown in FIG.
2
.
TABLE 1
Operation Mode
Vg
Vd
Vs
Vb
Programming
+10 V
+5 V~+6 V
0 V
0 V
Erasing
−10 V
floating
floating
+5 V
Reading
+4.5 V
+1 V
0 V
0 V
In a semiconductor memory device using NOR-type flash memory cells, programming and erasing operations are carried out by a command that is applied from an exterior of a chip. At this time, a verifying operation is carried out by an internal algorithm so that programmed or erased cell can have target program or erase threshold voltage distribution. If a cell is under or over a target threshold voltage, the cell is subject to a re-programming operation and a re-erasing or over-erase repair post-programming operation. An embedded algorithm for erasing a sector is classified into three parts that are a pre-programming algorithm as a first programming operation, a main erasing algorithm, and a post-programming algorithm as a second programming operation, as shown in FIG.
3
.
The embedded algorithm proceeds, as follows. In order to collect a threshold voltage distribution of an erased cell, all cells in a corresponding sector are sequentially programmed in the first programming operation to situate a threshold voltage of all cells in a sector, which will be erased, to a constant level (e.g., 7V or higher). A constant negative voltage (e.g., −10V) is then applied to all wordlines in the sector, erasing the cells at the same time as the main erasing operation. In this case, a constant positive voltage (e.g., 5V) is applied to not only a bulk of the corresponding sector but also a bulk of a cell in a redundancy field, erasing the cell at the same time as the cells in a main field. After the erasing operation, over-erased cells are detected to carry out a programming operation as the second programming operation for boosting up a voltage level thereof to a constant threshold voltage (e.g., 1V or higher) or higher.
Generally, a cell array of a NOR-type flash memory device is composed of redundancy fields for repairing cells whose programming and erasing operations are failed by hard defect and soft defect that occur in a main field and its cell array. In this case, a repaired unit is composed of row or wordline units or column or bitline units according to a core structure.
Cells causing a fail in a main field, which will hereinafter referred to as “defect cells”, are repaired by cells in a redundancy field, hereinafter referred to as “redundant cells”. In spite of the repair, the defect cells still remain in the main field, having an influence on operations of a memory device. In case of a wordline-related fail such as a wordline to bitline short, when a switch to decode a wordline is made using PMOS and NMOS transistors, a positive high voltage applied to a bulk during the erasing operation is equivalently applied to a gate. Thus, a voltage applied toward a drain of a PMOS transistor used in a conventional decoder is higher than that of a bulk in the PMOS transistor. A forward bias is then applied to a P-N junction. If a wordline is electrically connected to a bulk, the forward bias is also applied to a PMOS transistor junction used in a decoder. Accordingly, a wordline repair operation cannot be carried out in such a structure with an erasing operation is carried out by applying a bias to a bulk. This will be explained later in detail.
FIG. 4
schematically shows a 16M NOR-type flash memory device in accordance with a prior art. Also,
FIG. 5
shows a wordline select signal in accordance with a prior art. In a 16M NOR-type flash memory device, to select one wordline during reading or programming operation, one sector is selected by a sector address. Generally, one sector has a storage capacity of 64 KB and is composed of 1024 wordlines and 512 bitlines. To decode 1024 wordlines after selecting one sector, conceptually, a 10-bit address is required. The 10-bit address is divided into a first address A
0
-A
6
and a second address A
7
-A
9
, which are composed of seven address bits and three address bits, respectively.
Based on the first address, one of first select signals nSSi (i=0-127) for each selecting 128 selectors is activated. Also, based

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