Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-07-23
1998-06-16
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518501, 36518528, 36518514, 36518526, 365182, G11C 1134
Patent
active
057681929
ABSTRACT:
A novel apparatus for and method of programming and reading a programmable read only memory (PRON) having a trapping dielectric sandwiched between two silicon dioxide layers is disclosed that greatly reduces the programming time of conventional PROM devices. Examples of the trapping dielectric are silicon oxide-silicon nitride-silicon oxide (ONO) and silicon dioxide with buried polysilicon islands. A nonconducting dielectric layer functions as an electrical charge trapping medium. This charge trapping layer is sandwiched between two layers of silicon dioxide acting as an electrical insulator. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. For the same applied gate voltage, reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region.
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Nguyen Viet Q.
Saifun Semiconductors Ltd.
Zaretsky Howard
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