Non-volatile semiconductor memory cell

Details Non-volatile semiconductor memory cell Non-volatile semiconductor memory cell

1992-12-28

1994-04-12

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 257314, 257365, 257528, H01L 2968, G11C 1134

Patent

active

053031873

ABSTRACT:
A non-volatile semiconductor memory cell comprises a P-type semiconductor substrate (5) and N+ diffusion regions (6) spaced apart from each other on the principal surface of a P-type substrate (5). Each N+ diffusion region (6) can be used as source or drain of a transistor. Between any two adjacent N+ diffusion regions and under the gates is located the channel region (7). A control Y gate (8) is formed on an insulation layer above a portion of the channel and extends over a portion of N+ diffusion region (6). A floating gate (9) is formed on an insulation layer above the control Y gate (8) and the rest of the channel, and extends over a portion of another N+ diffusion region (6). A control X gate (10) is formed on an insulation layer above the floating gate (9) and N+ diffusion regions (6). Isolation between N+ diffusions (6), not covered by the control X gate (10), is provided by P+ diffusion regions (11) diffused into the substrate between each cell and its adjacent cells, or by oxide filled trench, or by relatively thick field oxide. The resulting structures are reliable contactless EPROM's or EEPROM's.

REFERENCES:
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 5057886 (1991-10-01), Riemenschneider et al.
patent: 5194925 (1993-03-01), Ajika et al.

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