Static information storage and retrieval – Floating gate – Multiple values
Patent
1996-12-27
1998-08-18
Nelms, David C.
Static information storage and retrieval
Floating gate
Multiple values
36518523, 36518524, G11C 1606
Patent
active
057966524
ABSTRACT:
A non-volatile semiconductor memory configured to be able to write a multi-value information into a memory cell, comprises a memory cell array composed of a number of memory cell transistors. First and second write circuits receive first and second quaternary input data, and generate first and second writing bit line voltages having a level corresponding to the value of the first and second quaternary input data, respectively. A column selection circuit selects first and second bit lines from a number of bit lines of the memory cell array, in accordance with a row address signal, and for simultaneously supplies the first and second writing bit line voltages to the selected first and second bit lines, respectively, at the time of the writing. Thus, two items of quaternary data can be simultaneously written into two memory cell transistors included in memory cell transistors of one row selected by one word line.
REFERENCES:
patent: 5412601 (1995-05-01), Sawada et al.
patent: 5487034 (1996-01-01), Inoue
patent: 5627781 (1997-05-01), Hayashi et al.
Sugawara Hiroshi
Takeshima Toshio
Mai Son
NEC Corporation
Nelms David C.
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