Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
1999-08-11
2001-05-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S226000
Reexamination Certificate
active
06233168
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to non-volatile semiconductor memory, more particularly to arrangement structures of a memory matrix for which a contrived method for reading data from the non-volatile semiconductor storage apparatuses is provided.
In a semiconductor storage apparatus, memory cells that can be set to three or more storage states are called multi-valued cells. For example, in a memory cell transistor, a multi-valued cell capable of storing 2-bit information by making it possible to set four values of current requires only half the cell area compared with a standard memory cell capable of storing 1-bit information. Such a multi-valued cell has an advantage in cost. However, since a multi-valued cell has several storage states, the gap between characteristic values in each state is smaller compared with the standard memory cell. Therefore, variations in the finished dimensions of the manufactured memory cells cause a high defective rate for the memory cells.
For this reason, in determining the arrangement structure of a multi-valued cell, it is important to apply a voltage to each terminal of a selected memory cell independently of the position of the selected memory cell within the arrangement. It is also desirable that the amount of parasitic current, which a sense amplifier detects, be made as small as possible. Here, the parasitic current is a current that depends on the data stored in adjacent cells other than the selected cell.
The arrangement structure of a multi-valued cell that avoids a parasitic current is disclosed in the Japanese Patent Application Laid-Open No. H6-318683. According to this arrangement structure, memory cells arranged in the column direction are divided into groups of eight memory cells which are electrically separated from each other. These eight memory cells which are electrically separated from each other are connected to main bit lines and main ground lines only when these eight memory cells are selected. When these eight memory cells are not selected, these electrically separated eight memory cells are electrically separated from the main bit lines and main ground lines, and are put in a floating state.
However, when a memory cell column is electrically separated for every eight cells, the area of the memory cell arrangement is increased. For example, when an electric separation means is constructed having an area equal to the area of one memory cell, the area of the resultant memory arrangement is increased by 12.5%. In addition, since unselected main bit lines and unselected main ground lines are put in a floating state, the access time is delayed, which is a problem.
SUMMARY OF THE INVENTION
Given these problems, it is an object of the present invention to provide a non-volatile semiconductor storage apparatus capable of reducing the amount of parasitic current as much as possible without using an electric separation means. It is also an object of the present invention to provide a non-volatile semiconductor storage apparatus which prevents unselected memory cells on selected row lines from being connected to selected column lines to the greatest extent.
According to the present invention, this non-volatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors whose gates are connected to word lines, respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines which connect the connection nodes between the sources and drains of the memory cell transistors in the column direction, a power source line which supplies a prescribed electric potential to these column lines, first and second sense amplifiers which detect the electric potential level of the column lines or a current that flows through the column lines, sense column line selection means which connect column lines connected to one terminal of one selected memory cell and one terminal of the other selected memory cell, respectively, to the first and second sense amplifiers, respectively. In this case, the one memory cell is separated from the other memory cell by a prescribed number of memory cells on the same memory cell row. This nonvolatile semiconductor storage apparatus further has power source supply column line selection means which connect the column lines connected to the other terminals of the two selected memory cells to the power source line.
It is desirable that the value of resistance of a wire path between the selected memory cell governed by the sense column line selection means and the first or second sense amplifier be smaller than the values of resistance of the prescribed number of memory cells.
REFERENCES:
patent: 5132933 (1992-07-01), Schreck et al.
patent: 2-210694 (1990-08-01), None
Ashizawa Yuichi
Kitazawa Shooji
Kokubun Hitoshi
Takeda Keiichiro
Jones Volentine, LLC
Lam David
Nelms David
OKI Electric Industry Co., Ltd.
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