Non-volatile semiconductor memory array structure and...

Details Non-volatile semiconductor memory array structure and... Non-volatile semiconductor memory array structure and...

2005-10-11

2005-10-11

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S051000, C365S063000, C365S072000

Reexamination Certificate

active

06954376

ABSTRACT:
A non-volatile memory array structure, comprising a plurality of first transistors, serving for memory function, being arranged to have a plurality of columns and a plurality of first rows. The first transistors in each column are coupled in series, and adjacent two of the columns are grouped into a memory group using a common bit line. The gate electrodes of the first transistors in the same first row are coupled with a first sequence word line. A plurality of second transistors are also included. Each of the second transistors is coupled between two columns of the memory group and is adjacent to each of the first rows. The second transistors form a plurality of second rows, wherein gate electrodes of the second transistors in the same second row are coupled to a second sequence word line.

REFERENCES:
patent: 5303184 (1994-04-01), Noda
patent: 5557569 (1996-09-01), Smayling et al.
patent: 6008516 (1999-12-01), Mehrad et al.
patent: 2004/0071011 (2004-04-01), Nishizaka et al.

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