Non-volatile semiconductor memory apparatus

Details Non-volatile semiconductor memory apparatus Non-volatile semiconductor memory apparatus

1998-03-27

2001-09-04

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190

Reexamination Certificate

active

06285589

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory apparatus in which multi-value data can be stored using memory cell transistors with floating gate electrodes.
2. Description of the Prior Art
In a programmable ROM (EEPROM: Electrically Erasable Programmable ROM) which has multiple memory cells, each comprising a single transistor, and which is capable of electrically erasing data stored in the memory cells, each memory cell comprises a double-gate transistor which has a floating gate electrode and a control gate electrode. A memory cell transistor with this type of double-gate structure writes data by accelerating hot electrons, generated on the drain region side of the control gate electrode, and injecting them into the floating gate electrode. Data is read out by detecting the difference in the operating characteristics of the memory cell transistor when electrical charge is injected at the floating gate electrode and when no charge being is injected.
FIG. 1
shows a front view of a memory cell portion of a conventional non-volatile semiconductor memory apparatus having floating gate electrodes, and
FIG. 2
, a cross-sectional view taken along the line X—X. These diagrams show a split gate structure wherein a portion of a control gate electrode is provided alongside a floating gate electrode.
A plurality of separate regions, comprising strips of oxide film (LOCOS) having selected thicknesses, are disposed on the surface of a P-type silicon substrate
1
, the element regions being partitioned. Floating gate electrodes
4
are disposed on the silicon substrate
1
, with oxide films
3
provided therebetween, so as to straddle adjacent separating regions
2
. Each of the floating gate electrodes
4
is provided independently for one memory cell. And, thick oxide films
5
are disposed above the centers of the floating gate electrodes
4
, at acute angles to the ends of the floating gate electrodes
4
, in order to increase electromagnetic concentration at the ends of the floating gate electrodes
4
when data is erased. Control gate electrodes
6
are disposed on the silicon substrate
1
, with one control gate electrode
6
corresponding to each row of multiple floating gate electrodes
4
. One part of the control gate electrode
6
overlaps the floating gate electrodes
4
, and the remaining part is disposed over the silicon substrate
1
with the oxide film
3
therebetween. Further, adjacent rows of floating gate electrodes
4
and control gate electrodes
6
are provided so that their surfaces are symmetrical to each other. Multiple N-type first diffusion layers
7
and N-type second diffusion layers
8
are provided in the substrate regions between the control gate electrodes
6
and the substrate regions between the floating gate electrodes
4
. The first diffusion layers
7
are provided independently between the control gate electrodes
6
and are separated by the separating regions
2
. By contrast, the second diffusion layers
8
continue parallel to the lengths of the control gate electrodes
6
. Thus, each memory cell transistor comprises a floating gate electrode
4
, a control gate electrode
6
, a first diffusion layer
7
and a second diffusion layer
8
. Aluminium lines
10
are provided over the control gate electrodes
6
, with an oxide layer therebetween, so as to intersect with the control gate electrodes
6
. The aluminium lines
10
pass through control holes
11
and connect to the first diffusion layers
7
.
In a double-gate memory cell transistor of the above type, the ON resistance between the source and the drain fluctuates in accordance with the amount of charge which is injected to the floating gate electrode
4
. Therefore, the ON resistances of the memory cell transistors are individually varied by injecting separate charges into the floating gate electrodes
4
. The resulting differences in operating characteristics of the memory cell transistors correspond to data which are stored. For example, data of four values (equivalent to two bits) can be stored in one memory cell transistor by injecting charge to the floating gate electrode
4
in four steps and reading out the resistances of the memory cell transistor in four steps.
FIG. 3
is a circuit diagram showing the memory cell portion of FIG.
1
. As
FIG. 3
shows, four rows and four columns of memory cells are provided.
The control gate electrodes
6
of the double-gate memory cells
20
are connected to word lines
21
, and the first diffusion layers
7
and the second diffusion layers
8
are connected to bit lines
22
and source lines
23
respectively. The bit lines
22
connect, via selective transistors
24
, to a data wire
25
, which is connected to a read load resistor
26
. The source lines
23
connect to a power line
27
. A write clock &phgr;W is applied along the power line
27
to each of the source lines
23
, and a read clock &phgr;R is applied from the data wire
25
, via the read load resistor
26
, to each of the bit lines
22
.
Normally, the control gate electrodes
6
, which are provided along each row of memory cell transistors
20
, function as the word lines
21
, and the aluminium lines
10
, which are connected to the first diffusion layers
7
, function as the bit lines
22
. Furthermore, the second diffusion layers
8
, which run parallel to the control gate electrodes
6
, are used as the source lines
23
.
Row selecting signals LS
1
~LS
4
, which are based on row address data, activate specific wires of the memory cell transistors
20
by selecting one of the word lines
21
.
Column selecting signals CS
1
~CS
4
, which are based on column address data, activate specific columns of the memory cell transistors
20
by switching one of the selective transistors
24
ON. Thus, by means of row address data and column address data, it is possible to specify any one of the multiple memory cell transistors arranged in columns and rows, and to connect the specified transistor to the data wire
25
.
Data is written into the memory cell transistors
20
by injecting charge to the floating gate electrodes
4
. More concretely, a ground potential (for instance, 0V) is applied from the data wire
25
to the memory cell transistors
20
, while a write power potential (for instance, 12V) is applied from the power line
26
to the memory cell transistors
20
. As a result, data is written (i.e. charge is injected to the floating gate electrode
4
) at the memory cell transistor
20
which has been activated by the selecting signals LS
1
~LS
4
and CS
1
~CS
4
. Also, data is read out from the memory cell transistors
20
by detecting the resistances when the memory cell transistors
20
have been switched ON. More concretely, a power potential for reading (for instance, 2V) is applied to the memory cell transistors from the data wire
25
and a ground potential (for instance, 0V) is applied to the memory cell transistors
20
from the power line
26
. Here, sense amplifiers (not shown in the diagram), which are connected to each of the bit lines
22
, detect the ON resistances of the memory cell transistors
20
.
In order to improve recording precision when writing multi-value data (or analog data) into the memory cell transistors
20
, the operations of charge injection (writing) and identification of charge amounts (reading) are performed repeatedly in short cycles. In other words, data are gradually written to the memory cell transistors
20
while simultaneously being read, and the writing ends when the data which have been read out match the contents of the data being recorded.
FIG. 4
depicts waveforms for the write clock &phgr;W and the read clock &phgr;R. As
FIG. 4
shows, the write clock &phgr;W is, for instance, set to rise only during fixed periods in a fixed cycle, and is applied to the memory cell transistors
20
from the power line
27
via the source lines
23
. Then, the data wire
25
is lowered to ground potential in synchronism with the write clock &phgr;W. Therefore, during the peri

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