Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-07-21
2001-07-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185190, C365S185120
Reexamination Certificate
active
06266270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilevel non-volatile semiconductor memory for recording data of at least three levels to a memory cell and a method of writing the data.
2. Description of the Related Art
In non-volatile semiconductor memory apparatuses such as flash memories, a two-level memory cell structure is normally adopted, which records data having two values, “0” and “1”, in one memory cell transistor.
Along with the recent demands for larger capacities of semiconductor memories, a so-called multilevel non-volatile semiconductor memory which records data of at least 3 levels in one memory cell has been proposed (for example, refer to “A Multi-Level 32 Mb Flash Memory” 1995 ISSCC, from p. 132).
FIG. 1
is a view of the relationship of a level of a threshold voltage Vth and data contents when recording data composed of 2 bits having four values in one transistor in a NAND flash memory.
In
FIG. 1
, the ordinate indicates the threshold voltage Vth and the abscissa indicates a distribution frequency of a memory transistor.
The two-bit data comprising the data to be recorded in one transistor is indicated by (IO
n+1
, IO
n
). There are four states (IO
n+1
, IO
n
)=(1, 1), (1, 0), (0, 1), and (0, 0). Namely, there are four states of the data “0”, data “1”, data “2”, and data “3”.
Also, a NAND flash memory has been proposed which performs a write operation of multi-level data in page units (word line units) (for example, refer to 1996 IEEE International Solid-State Circuits Conference, ISSCC96/SESSION 2/FLASH MEMORY/PAPER TP 2.1:A 3.3V 128 Mb Multi-Level NAND Flash Memory For Mass Storage Application, pp. 32 to 33).
FIG. 2
is a circuit diagram of the configuration of the core part of a NAND flash memory for performing a write operation in page units disclosed in the above reference.
In
FIG. 2
, reference number
1
indicates a memory cell array,
2
a write/read control circuit, and BL
1
and BL
2
bit lines.
The memory cell array
1
comprises memory strings A
0
and A
1
comprising memory cells respectively connected to common word lines WL
0
to WL
15
. The memory string A
0
is connected to the bit line BL
1
and the memory string A
1
is connected to the bit line BL
2
.
The memory string A
0
has a NAND string comprised of serially connected memory cell transistors MT
0
A to MT
15
A comprising non-volatile semiconductor memories having floating gates. A drain of the memory cell transistor MT
0
A of the NAND string is connected to the bit line BL
1
via a select gate SG
1
A, while a source of the memory transistor MT
15
A is connected to the reference potential line VGL via a select gate SG
2
A.
The memory string A
1
has a NAND string comprised of serially connected memory cell transistors MT
0
B to MT
15
B comprising non-volatile semiconductor memories having floating gates. A drain of the memory cell transistor MT
0
B of the NAND string is connected to the bit line BL
2
via a select gate SG
1
B, while a source of the memory transistor MT
15
B is connected to the reference potential line VGL via a select gate SG
2
B.
Gates of the select gates SG
1
A and SG
1
B are commonly connected to a select signal supply line SSL, while gates of the select gates SG
2
A and SG
2
B are commonly connected to a select signal supply line GSL.
The write/read control circuit
2
comprises n-channel MOS (NMOS) transistors NT
1
to NT
17
, a p-channel MOS (PMOS) transistor PT
1
, and latch circuits Q
1
and Q
2
combining inputs and outputs of an inverter.
The NMOS transistor NT
1
is connected between a supply line of a power source voltage Vcc and the bit line BL
1
and the gate is connected to a supply line of an inhibit signal IHB
1
. The NMOS transistor NT
2
is connected between the supply line of the power source voltage Vcc and the bit line BL
2
and the gate is connected to a supply line of an inhibit signal IHB
2
.
A depletion NMOS transistor NT
18
is connected between a connecting point of an NMOS transistor NT
3
and an NMOS transistor NT
1
and a connecting point of the memory string A
0
and the bit line BL
1
. A depletion NMOS transistor NT
19
is connected between a connecting point of an NMOS transistor NT
4
and an NMOS transistor NT
2
and a connecting point of the memory string A
1
and the bit line BL
2
. Gates of the NMOS transistors NT
18
and NTl
9
are connected to a decouple signal supply line DCPL.
NMOS transistors NT
3
, NT
5
, and NT
16
are connected in series between a connecting point of the depletion NMOS transistor NT
18
and the NMOS transistor NT
1
and a bus line IOi, while NMOS transistors NT
4
, NT
7
, and NT
17
are connected in series between a connecting point of the depletion NMOS transistor NT
19
and the NMOS transistor NT
2
and a bus line IO
i+1
.
Also, a connecting point of the NMOS transistors NT
3
and NT
5
and a connecting point of the NMOS transistors NT
4
and NT
7
are grounded via an NMOS transistor NT
6
and connected to a drain of the PMOS transistor PT
1
and gates of NMOS transistors NT
8
and NT
13
. A gate of the NMOS transistor NT
6
is connected to a supply line of a reset signal RST, a source of the PMOS transistor PT
1
is connected to a supply line of the power source voltage Vcc, and a gate of the PMOS transistor PT
1
is connected to a supply line of a signal Vref.
A first memory node N
1
a
of the latch circuit Q
1
is connected to a connecting point of NMOS transistors NT
5
and NT
16
, while a second memory node N
1
b
is grounded via NMOS transistors NT
8
to NT
10
connected in series.
A first memory node N
2
a
of the latch circuit Q
2
is connected to a connecting point of the NMOS transistors NT
7
and NT
17
, while a second memory node N
2
b
is grounded via NMOS transistors NT
13
to NT
15
.
A connecting point of the NMOS transistors NT
8
and NT
9
is grounded via the NMOS transistors NT
11
and NT
12
connected in series.
A gate of the NMOS transistor NT
9
is connected to a first memory node N
2
a
of the latch circuit Q
2
, a gate of the NMOS transistor NT
10
is connected to a supply line of a control signal (&phgr;LAT
2
, a gate of the NMOS transistor NT
11
is connected to a second memory node N
2
b
, a gate of the NMOS transistor NT
12
is connected to a supply line of a control signal &phgr;LAT
1
, and gates of the NMOS transistors NT
14
and NT
15
are connected to a supply line of a latch control &phgr;LAT
3
.
A gate of the NMOS transistor NT
16
serving as a column gate is connected to a supply line of a signal Yi and a gate of the NMOS transistor NT
17
is connected to a supply line of a signal Yi+1.
FIG. 3A
is a timing chart at the time of reading and
FIG. 3B
is a timing chart at the time of writing (programming).
As will be understood from
FIG. 3B
, writing of four values is carried out in three steps. The procedure moves on to the next step at the stage when it is judged that all cells to which the write operation was originally to be performed in page units in each of the steps are sufficiently written in.
A read operation will be explained next.
First, a reset signal RST and signals PGM
1
and PGM
2
are set at a high level. Due to this, the first memory nodes N
1
a
and N
2
a
of latch circuits Q
1
and Q
2
are drawn to the ground level. As a result, the latch circuits Q
1
and Q
2
are cleared.
Next, a word line voltage is made to be 2.4V and a read operation is performed. The bit line voltage is held at a precharge voltage due to the fact that a cell current does not flow when the threshold voltage Vth is higher than the word line voltage (2.4V), and a high level is sensed. Conversely, when the threshold voltage Vth is lower than the word line voltage (2.4V), a cell current flows, so that the bit line voltage falls and a low level is sensed.
Next, a read operation is carried out when the word line voltage is at 1.2V, then, finally, at 0V.
Specifically, since a current does not flow in any word lines when the cell data is “00”, (1, 1) is output to buses IO
i+1
and IO
i
. First, when the word li
Kananen Ronald P.
Le Vu A.
Nguyen Vanthu
Rader Fishman & Grauer
Sony Corporation
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