Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1999-02-17

2000-12-05

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular connection

36518513, 36518525, G11C 1604

Patent

active

061575690

ABSTRACT:
A memory cell array 11 is divided into plural blocks in such a manner that a first and a second split bit line BLa and BLb0 are provided for a single main bit BL0. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. Further, on both sides of the memory cell array, a wiring 20 at a predetermined potential ARGND and wirings 21 and 22 for select control signals DCBLa and DCBLb are arranged. A second gate electrode wiring 23 connects the gate of the first select transistor Q0, that of the second discharge transistor (corresponding to Q3) relative to the adjacent main bit line and the wiring 21. A first gate electrode wiring 25 connects the gate of the second select transistor Q1, that of the first discharge transistor Q2 and the wiring 21. In such a configuration, the capacity of a non-volatile semiconductor memory is increased so that the capacitive load of bit lines can be reduced and the operation speed can be enhanced. The increase in the chip size can be prevented and easiness of the layout of the pattern of the memory can be assured.

REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 5761119 (1998-06-01), Asano

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