Non-volatile semiconductor memory

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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C365S230080

Reexamination Certificate

active

11283853

ABSTRACT:
A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells via the bit lines; a shield power supply providing a voltage to shield the bit lines; and a bit line selection circuit, configured to connect even bit lines to the shield power supply when odd bit lines are connected to the sense amplifier, and to connect the odd bit lines to the shield power supply when the even bit lines are connected to the sense amplifier.

REFERENCES:
patent: 5805498 (1998-09-01), Lee et al.
patent: 6058044 (2000-05-01), Sugiura et al.
patent: 6649945 (2003-11-01), Hosono et al.
patent: 6813187 (2004-11-01), Lee
patent: 6813214 (2004-11-01), Cho et al.
patent: 6839276 (2005-01-01), Sugiura et al.
patent: 7177196 (2007-02-01), Takeuchi et al.
patent: 11-176177 (1999-07-01), None

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