Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

2001-09-24

2003-04-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S072000, C257S300000, C257S314000, C257S319000, C257S390000, C257S391000

Reexamination Certificate

active

06545893

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and, in particular, to a structure of a NROM (nitride read only memory) type non-volatile semiconductor memory.
2. Description of the Background Art
FIG. 61
is a top view illustrating part of the structure of a conventional NROM type non-volatile semiconductor memory, and it schematically shows only the arrangement of word lines WL
1
and WL
2
, bit lines BL
1
and BL
2
, and channel regions CH
1
to CH
3
. The word lines WL
1
and WL
2
extend in a predetermined direction (hereinafter referred to as “row direction”). The bit lines BL
1
and BL
2
extend in a direction orthogonal to the row direction (hereinafter referred to as “column direction). The channel regions CH
1
to CH
3
are disposed between bit lines adjacent with each other, and extend in the column direction.
FIG. 62
is a sectional view of a memory cell transistor structure, corresponding to a cross-sectional structure taken along the line A
1
—A
1
in FIG.
61
. LOCOS (local oxidation of silicon) type isolation insulating films
106
12
and
106
23
for defining an element-forming region are selectively formed in the upper surface of a silicon substrate
101
. N
+
type impurity diffusion regions
107
12
and
107
23
are formed at the interfacial portions between the silicon substrate
101
and the isolation insulating films
106
12
and
106
23
. The impurity diffusion regions
107
12
and
107
23
correspond to the bit lines BL
1
and BL
2
shown in FIG.
61
. The impurity diffusion regions
107
12
and
107
23
can be formed by introducing, by ion implantation method, an n-type impurity into the silicon substrate
101
beneath the isolation insulating films
106
12
and
106
23
, and then subjecting the impurity to thermal diffusion.
ONO films
105
1
to
105
3
are formed on the upper surface of the silicon substrate
101
in the element-forming region. The ONO films
105
1
to
105
3
extend so as to overlie the end portions of the isolation insulating films
106
12
and
106
23
. The ONO films
105
1
to
105
3
have such a three-layer structure that silicon oxide films
102
1
to
102
3
, silicon nitride films
103
1
to
103
3
, and silicon oxide films
104
1
to
104
3
are formed in this order on the silicon substrate
101
. Unlike MNOS (metal nitride oxide semiconductor) type memory cell transistors, the silicon oxide films
102
1
to
102
3
and
104
1
to
104
3
have a thickness of not less than 5 nm, in order to prevent tunneling phenomenon of electrons.
A conductive film
109
1
is disposed on the ONO films
105
1
to
105
3
and the isolation insulating films
106
12
and
106
23
. The conductive film
109
1
has, for example, polycide structure or polymetal structure. For the purpose of increasing the operation speed of memory cell transistors, it is preferable to employ polymetal structure having lower resistance than polycide structure. The conductive film
109
1
corresponds to the word line WL
1
shown in FIG.
61
. P-type channel regions
108
1
to
108
3
are disposed in the upper surface of the silicon substrate
101
in the element-forming region. The channel regions
108
1
to
108
3
correspond to the channel regions CH
1
to CH
3
shown in FIG.
61
. By adjusting the impurity concentration of the channel regions
108
1
to
108
3
, the threshold voltage of the memory cell transistor can be set to a desired value.
The impurity diffusion regions
107
12
and
107
23
function as the source/drain regions of the memory cell transistors. The ONO films
105
1
to
105
3
function as the gate insulating film of the memory cell transistors. The conductive film
109
1
overlying the ONO films
105
1
to
105
3
functions as the gate electrode of the memory cell transistors.
The isolation insulating films
106
12
and
106
23
are formed in the following manner. First, an ONO film is formed on the entire upper surface of a silicon substrate
101
. The ONO film is then patterned to form ONO films
105
1
to
105
3
, thereby to expose part of the upper surface of the silicon substrate
101
. The exposed part of the silicon substrate
101
is then subjected to thermal oxidation, thereby forming isolation insulating films
106
12
and
106
23
. Thus, by arranging such that the ONO films
105
1
to
105
3
function as an oxidation preventing mask in forming the isolation insulating films
106
12
and
106
23
, in addition to the function of the gate insulating film of the memory cell transistor, the number of manufacturing steps can be reduced.
An NROM type non-volatile semiconductor memory, as will be described below, can store a 2-bit information in total, a 1-bit for each of two locations in one memory cell transistor. Referring to
FIG. 61
, the unit cell area of the NROM type non-volatile semiconductor memory is 2F×2.5F=5F
2
, wherein F (featured size) corresponds to a design rule. When F=0.35 &mgr;m, 5F
2
=0.6125 &mgr;m
2
. When F=0.25 &mgr;m, 5F
2
=0.3125 &mgr;m
2
. The NROM type non-volatile semiconductor memory can be manufactured relatively easily only by adding four photomasks (two of which are for memory cell, and the remainder for peripheral circuit) to existing CMOS process. For the reason for this, the NROM type non-volatile semiconductor memory has the features of having high storage density and low manufacturing cost.
The operation of a NROM type memory cell transistor will now be fully described. The NROM type memory cell transistor can store a 1-bit information at each of two locations of one memory cell transistor. In the present specification, one location storing information is defined as “Bit R”, and the other location is defined as “Bit L”.
FIGS.
63
(A) and
63
(B) are schematic diagrams illustrating write operation. FIG.
63
(A) shows the write operation to the Bit R. A voltage of V
S
=0 V is applied to an impurity diffusion region
107
12
functioning as a source region, a voltage of V
D
=4 V is applied to an impurity diffusion region
107
23
functioning as a drain region, and a voltage of V
G
=8 V is applied to a gate electrode
109
1
. Thereby, channel hot electrons are introduced via a silicon oxide film
102
2
into a silicon nitride film
103
2
, and the introduced electrons are then trapped and stored by traps (also called trap levels or trap centers) which are discretely distributed in the silicon nitride film
103
2
. Unlike electrons stored in a floating gate such as of a flash memory, the electrons stored in the silicon nitride film
103
2
are less dispersible in a lateral direction (the gate length direction) in the silicon nitride film
103
2
. The number of electrons needed in writing is as few as 200 to 500, and writing is completed in a short time of about 100 ns. By reversing the voltages applied to the impurity diffusion regions
107
12
and
107
23
, writing to the Bit L can be performed as shown in FIG.
63
(B).
FIGS.
64
(A) and
64
(B) are schematic diagrams illustrating erase operation. FIG.
64
(A) shows an erase operation related to the Bit R. A voltage of V
SD12
=0 V is applied to the impurity diffusion region
107
12
, a voltage of V
SD23
=4 V is applied to the impurity diffusion region
107
23
, and a voltage of V
G
=−6 V is applied to the gate electrode
109
1
. Thereby, there occurs a potential difference between the silicon substrate
101
(or the channel region
108
2
) and the impurity diffusion region
107
23
. As a result, the energy bands of the silicon substrate
101
is curved, and interband tunnel current flows. By the interband tunnel current, hot holes are induced, and the hot holes are attracted by the gate voltage of −6 V and then introduced into the silicon nitride film
103
2
via the silicon oxide film
102
2
. The introduced holes are then coupled to electrons stored in the silicon nitride film
103
2
, thereby erasing the stored information of the Bit R. Since the number of electrons to be erased is s

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