Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1999-08-17

2002-02-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C385S105000, C385S105000, C385S105000

Reexamination Certificate

active

06349061

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory, such as an EPROM (Erasable and Programmable ROM), or EEPROM (referred to as Electrical Erasable and Programmable ROM, flash EEPROM, or flash memory), in which data are stored (written/read) by accumulating charges in a floating gate and detecting a change in a threshold voltage in terms of the presence or absence of the charges by a control gate.
2. Description of the Related Art
A technique of using a redundant memory cell built in a semiconductor memory in place of a memory cell which cannot be used because of its defect has been developed. The address of a defective memory cell can be known in the process of manufacturing the semiconductor memory. The address of the defective memory cell is stored previously in a redundant address. It is always observed whether or not the address generated from a normal address generating circuit is that of the defective cell. If so, the redundant memory cell is addressed in place of the defective memory cell. Namely, the address line having the defective memory cell is not used.
FIG. 3
is a circuit showing a part of an addressing circuit
1
of the semiconductor memory having such a redundancy function.
An address data for addressing is applied to the address generating circuit
1
. An address data of a defective memory cell, which can be known from a test during the manufacturing process of the semiconductor memory cell, is applied to a redundant address generating circuit
2
. A comparator
3
compares an output signal from the address generating circuit and that from the redundant address generating circuit
1
. In this case, it generates a “H” level signal when the address data of the defective memory cell is generated from the address generating circuit
1
, and an “L” level signal in other cases. A first switching means determines whether or not the output signal from the address generating circuit
1
should be selected according to the output from the comparator
3
. Each of decoders decodes the address data from the first switching means
4
. The decoding intends to designate the normal memory cell, or to designate the defective memory cell, i.e. to decode the address for redundancy. These decoders
5
A,
5
B,
5
C and
5
D are connected to word lines WL
0
, WL
1
, WL
2
and WL
3
, respectively. Although not shown, a larger number of decoders and WL's are actually connected.
When the normal address, but not redundant address is generated, the output signal from the address generating circuit
1
is applied to the decoders
5
A,
5
B,
5
C and
5
D through the first switching means
4
. The output from the decoder corresponding to the selected WL becomes “L” level. Thus, the memory cell is designated.
When the redundant address is generated from the address generating circuit
1
, the “H” level is generated from the comparator
3
so that the “L” level is applied to each of the AND gates constituting the first switching means
4
. Thus, the address from the address generating circuit
1
is not applied to the decoders
5
A,
5
B,
5
C and
5
D.
On the other hand, the “H” level from the comparator
3
is applied to an AND gate
6
so as to be conductive. The addressing signal from the redundant address generating circuit
2
is sent to a redundant word line RWL through the AND gate
6
so that the redundant memory cell can be addressed.
Accordingly, in the device as shown in
FIG. 3
, the redundant address can be designated.
However, where the above semiconductor memory is a non-volatile semiconductor memory called a flash memory, as the case may be, the following problem happened.
Now, referring to
FIG. 4
, an explanation will be given of such a non-volatile semiconductor memory. Although the non-volatile semiconductor memory cell is roughly classified into a split-gate type and a stacked-gate type, the split-gate type non-volatile semiconductor memory as disclosed in WO92/18980 (G11C13/00) will be explained.
FIG. 4
is a circuit diagram of a memory cell array
21
in which non-volatile memories
20
A,
20
B,
20
C and
20
D are arranged in a matrix form.
FIG. 5
is a view showing the structure of a certain memory cell therein.
As seen from
FIG. 4
, in adjacent non-volatile semiconductor memories
20
A and
20
B, and
20
C and
20
D, their source regions are commonly connected to a source line SL, and their drain regions are connected to bit lines BL
0
, and BL
1
, respectively. The control gates CG's of the non-volatile memories
20
A and
20
C, and
20
B and
20
D are connected to word lines WL
0
and WL
1
, respectively. In such a spirit gate structured non-volatile semiconductor memory, as shown in
FIG. 5
, since the control gate electrode CG is formed from on the upper surface of the floating gate electrode to on the side surface thereof, a distance between the control gate electrode CG and the bit lines becomes narrower. Therefore according to the progress of miniaturization of the device, the interval between the bit lines BL
0
, BL
1
and control gates CG's (word lines) becomes very narrow so that short-circuiting is likely to occur in comparison with the stacked gate structure in which control gate electrode is formed on the floating gate electrode. When the short-circuiting occurs, the memory at issue cannot be used and dealt with as a defective cell
An explanation will be given of the method of writing, reading or erasing data (charge) into or from the non-volatile semiconductor memory having such a structure. The following explanation will be particularly directed to the non-volatile semiconductor memory cell
20
A.
The writing operation is made as follows. The voltages of e.g. 0 V, 11V and 2V are applied to the bit line BL
0
, source line SL and word line WL
0
, respectively. In this case, since a high voltage is applied to the source line, the potential of a floating gate FG which is strongly capacitive-coupled with a diffused layer (not shown) constituting the source line is raised to about 9 V. As a result, hot electrons generated between the drain region and source region jump into the floating gate FG, thus making the data writing operation.
The reading operation is made as follows. The voltages of e.g. 2 V, 0 V and 4 V are applied to the bit line BL
0
, source line SL and word line WL
0
, respectively. In this case, it is determined whether or not data. has been stored in the floating gate FG according to whether or not a reading operation current flows from the drain region to the source region. Specifically, when the reading operation current does not flow, the data has been stored in the floating gate. The erasure is made as follows. The voltages of e.g. 0 V, 0 V and 14 V are applied to the bit line BL
0
, source line SL and word line WL
0
, respectively. Then, the charge stored in the floating gate is pulled out toward the control gate CG so that the data is erased.
In the non-volatile semiconductor memory having the above structure, when all the word lines WL's must be simultaneously selected for data erasure, if there is any leaking defective cell, the high voltage (14 V in the above explanation) required for erasure cannot be supplied to each control gate CG.
In
FIG. 3
, all the decoders
5
A,
5
B,
5
C and
5
D are selected for data erasure. The high voltage from the high voltage generating circuit
8
is applied to the word lines WL
0
, WL
1
, WL
2
and WL
3
through the decoders
5
A,
5
B,
5
C and
5
D, respectively. If there is leakage failure in any memory cell (cell directed to redundancy) connected to the word lines WL
0
, WL
1
, WL
2
and WL
3
, the voltage on these word lines cannot be raised to about 14 V. Therefore, erasure cannot be normally made for all the memory cells connected to WL
0
, WL
1
, WL
2
and WL
3
.
Now, the leakage failure refers to short-circuiting in the word line WL's that is a phenomenon that excessive current flows through the word line WL. This is attribut

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