Non volatile semiconductor, memory

Details Non volatile semiconductor, memory Non volatile semiconductor, memory

2000-03-30

2001-05-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185230, C365S185290

Reexamination Certificate

active

06233174

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is related to a semiconductor device having a non-volatile storage element capable of storing at least 4 values of information (namely, 2 bits of information) into a single memory cell, for example, an electrically reprogramable non-volatile semiconductor memory device such as a flash memory, and furthermore, is related to a technique effectively applicable to a data processing system such as a file memory system with using this non-volatile semiconductor memory device.
Conventionally, non-volatile semiconductor storage devices such as flash memories have been proposed. These storage devices are capable of storing information by injecting and/or extracting electrons with respect to floating gates. A flash memory owns a memory cell transistor having a floating gate, a control gate, a source, and a drain. In this memory cell transistor, when electrons are injected into the floating gate, a threshold voltage would be increased, whereas when electrons are extracted from the floating gate, the threshold voltage would be decreased. The memory cell transistor may store therein information in response to the higher/lower threshold voltages with respect to a word line voltage (namely, voltage applied to control gate) used to read out data. Although not having restriction intentions, the lower threshold voltage condition of the memory cell transistor will be referred to as an “erasing state”, and the higher threshold voltage condition thereof will be referred to as a “writing state” in this specification.
Among these flash memories, such a flash memory is available that information having more than 4 values can be stored in a single memory transistor. For example, such multi-level memories are described in Japanese Publication “NIKKEI MICRODEVICE” issued in November, 1994, pages 48 to 49, and further Japanese laid-opened Patent Application No.9-297996/1997 opened in 1997.
SUMMARY OF THE INVENTION
In a multi-level memory, for example, if a selection can be made of one state from an erasing state and first to third writing states whose threshold voltages are different from each other with respect to this erasing state, then information having four values can be stored in a single memory cell transistor. If an erasing operation is carried out before a writing operation, then information having four values can be stored by determining that all of the first to third writing states is not selectable, or any one of the first to third programing states is selected. In this programing operation, such program control information is required so as to determine as to whether or not the programing operations are selected in order to separately obtain the first programing state through the third programing state. To save such program control information, a sense latch circuit and a data latch circuit, provided on each of bit lines, may be employed.
A sense latch circuit is constructed of, for example, a static latch. One end of each of bit lines is connected to a pair of input/output terminals of this sense latch circuit, and a drain of the above-described memory cell transistor is connected to each of these bit lines. Moreover, a data latch circuit is connected to the other end of each of bit lines. When either a readout voltage or a verify (verification) voltage is applied to a control gate of the memory cell transistor, the above-described sense latch circuit senses as to whether or not a current may flow through the source-to-drain path. At this time, the bit line provided on one operation non-selected side of the sense latch circuit is precharged to a reference level. Also, when data is written by forming a high potential difference between the control gate of the memory cell transistor and the drain thereof, the drain voltage is increased, or decreased every memory cell, so that it is possible to discriminate the program selection to the memory cell from the program non-selection to the memory cell. In this case, the sense latch circuit latches the data in correspondence with the program selection, and the program non-selection. This latched data corresponds to the above-explained program control information.
Such program control information is produced via a data converting circuit every 2 bits of externally supplied program data, and then is latched by the sense latch circuit of the program-selected bit line and by each of the data latch circuits for the bit line pair which commonly use this sense latch circuit. In the case that the programing operation is carried out in unit of a word line, the program control information is previously latched into the above-described sense latch circuit and data latch circuit as to all of bit lines. Which commonly use the word line.
In the programing operation, a decision is first made as to whether or not the memory cell is brought into the first program state in accordance with the program control information latched by the sense latch circuit. Next, another decision is made as to whether or not the memory cell is brought into the second program state in accordance with the program control information which has been internally transferred from one data latch circuit to the sense latch circuit. Moreover, a further decision is made as to whether or not the memory cell is brought into the third program state in accordance with the program control information which has been internally transferred from the other data latch circuit to the sense latch circuit. In this manner, the information having the four values specified by the 2-bit data can be stored into a single memory cell. In the above-explained programing operations from the first programing state to the third programing state, such a verify operation is carried out as to whether or not the threshold voltage of the memory cell reaches the threshold voltage allocated to each of the first to third programing states.
At this time, there is such a memory cell which is brought into an overprograming state among these memory cells with respect to each of the first to third programing states. In this memory cell, the threshold voltages under preceding/succeeding programing states cannot be discriminated from each other. For instance, the threshold voltage of the memory cell of the first programing state becomes high, which cannot be discriminated from the threshold voltage of the second programing state. In such a case, in order to retry the programing operation from the beginning stage, after the erasing operation is carried out with respect to the memory cell to be written, the above-explained programing operation is retried.
However, when the programing operations from the first programing state to the third programing state are once carried out, the program control information which has been first latched into the sense latch circuit would be overwritten by another program control information internally transferred from the data latch circuit to thereby disappear. As a result, when the reprograming operation is performed due to the overprograming operation, the same program data must be again received from the external device. To this end, the control circuit for access-controlling the flash memory must save the program data in a work memory or the like for the time being after the programing operation is carried out with respect to the flash memory. Thus, the work load for access-controlling the flash memory would also be increased. The Inventors could reveal that this fact may lower the access efficiency of the flash memory, or the data processing efficiency.
Furthermore, in such a case that the programing operation itself will finally fail due to the failure operation of the reprograming operation caused by the overprograming operation, it is imaginable that the program data existed in this failure programing operation is stored into another storage area of this flash memory, or another flash memory. Similar to the previous case, the flash memory related to this failure programing operation can no longer save the program data at this time. As a consequ

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