Non-volatile semiconductor latch using hot-electron...

Details Non-volatile semiconductor latch using hot-electron... Non-volatile semiconductor latch using hot-electron...

2004-12-10

2010-06-29

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S158000, C365S157000, C365S173000, C365S049130

Reexamination Certificate

active

07746695

ABSTRACT:
The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a μm BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash EEPROM. Suggested is a bi-stable latch circuit having a pair of cross-coupled branches (I,II), each branch including a complementary driver and a load connected between a drain line and a source line and a non-volatile memory cell having a program transistor and a read transistor, at least one of said drivers and loads including said read transistor, said driver and load of said branch connected in series at a respective output node, said read transistor and program transistor having a common floating gate and separate control gates, said control gate of said program transistor connected to a program voltage, the drain of said program transistor connected to a respective input node, said control gate of said read transistor in said branch connected to said output node of the other branch (II).

REFERENCES:
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patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 5428571 (1995-06-01), Atsumi et al.
patent: 5648930 (1997-07-01), Randazzo
patent: 5696455 (1997-12-01), Madurawe et al.
patent: 2054303 (1981-02-01), None
International Search Report mailed Mar. 23, 2005.

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