Non-volatile semiconductor device with an electrically erasable

Static information storage and retrieval – Floating gate – Particular biasing

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365218, G11C 1300

Patent

active

056005954

ABSTRACT:
A non-volatile semiconductor memory with an electrically erasable and programmable read only memory showing a high speed batch erasure operation is provided wherein applications of erasure pulse signals onto the memory cells are continued until the number of times of the erasure pulse signal applications made corresponds to a predetermined number already set before commencement of the erasure pulse signal applications, the predetermined number being set to correspond to an estimated number of times of the erasure pulse signal applications necessary for completing the batch erasure operation for subsequently repeating a set of an additional erasure pulse signal application onto the memory cells and a verifying process for verifying erasure states of all the memory cells until there is verified the fact that all the memory cells have been in erasure states.

REFERENCES:
patent: 5341339 (1994-08-01), Wells
patent: 5369615 (1994-11-01), Harari et al.
patent: 5410511 (1995-04-01), Michiyama

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